The use of of_property_read_bool() for non-boolean properties is
deprecated in favor of of_property_present() when testing for property
presence.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20241104190455.272527-1-robh@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.
Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.
Fixes: 35b97bb941 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
'struct ccu_reset_map' are not modified in these drivers.
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig, as an example:
Before:
======
text data bss dec hex filename
1533 2224 0 3757 ead drivers/clk/sunxi-ng/ccu-sun20i-d1-r.o
After:
=====
text data bss dec hex filename
1597 2160 0 3757 ead drivers/clk/sunxi-ng/ccu-sun20i-d1-r.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://patch.msgid.link/44745f27034fa670605cd16966a39b7fe88fe5a6.1726863905.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Allwinner has previously released a H616 audio driver which also
provides sigma-delta modulation for the audio PLL clocks. This approach
is used in other Allwinner SoCs, including the H3 and A64.
The manual-provided clock values are:
PLL_AUDIO(hs) = 24 MHz*N/M1
PLL_AUDIO(4X) = 24 MHz*N/M0/M1/P
PLL_AUDIO(2X) = 24 MHz*N/M0/M1/P/2
PLL_AUDIO(1X) = 24 MHz*N/M0/M1/P/4
A fixed post-divider of 2 is used to account for a M0 divider of
2, which cannot be modelled by the existing macros and ccu_nm struct.
Add SDM to the H616 clock control unit driver.
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Tested-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241023075917.186835-2-ryan@testtoast.com
[wens@csie.org: Fixed whitespace errors]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk driver support. We have the usual Qualcomm clk drivers, along with
clk drivers for the Sophgo and T-Head vendors, all to support some new
SoCs.
Nothing in particular stands out to me in the updates. There's the
interconnect clk driver which exposes clks as interconnects, crossing
subsystems. There's a bunch of janitorial things that are improving
drivers in general like kmemdup_array() or fixing error paths. But
overall the updates look normal to fix the description data which is
usually the stuff that's wrong and/or untested.
I really wanted to land a bunch of KUnit clk code that I've been working
on whenever I get some free time but it turned into a pumpkin at the
last minute so I dropped those patches. I'll let it soak in linux-next
after the merge window closes. I have a suspicion that we're going to
need to totally rework the clk framework to fix structural issues like
locking, clk rate setting, and runtime PM usage. Having a bunch of unit
tests for that will help make sure that all keeps working.
Core:
- Skip gate basic type KUnit tests on s390 due to lack of MMIO emulation
New Drivers:
- AP sub-system clock controller in the T-Head TH1520
- Sophgo Sophon sg2042 clk driver
- Qualcomm SM7150 camera, display and video clk drivers
- Qualcomm QCM2290 GPU clk driver
- Qualcomm QCS8386/QCS8084 NSS clk driver
- Qualcomm SM8650 camera and video drivers
Updates:
- Add reset support to Airoha EN7581 clk driver
- Add MODULE_DESCRIPTIONs to various clk drivers
- Introduce helper logic to expose clock controllers as simple
interconnect providers
- Use the interconnect helper above on Qualcomm ipq9574
- Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm
X1Elite
- Improve error handling in Qualcomm kpss-xcc driver
- Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
- Export more clocks for Rockchip rk3128 peripherals
- Convert Rockchip clk drivers to use kmemdup_array()
- Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
- Make qcom_cc_really_probe() take a struct device to allow reuse in
non-platform-drivers
- Introduce prepare-only branch clock ops in the qcom clk driver to
support clocks on buses that take locks
- Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
- Support Qualcomm Huayra 2290 alpha PLL
- Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match
HS200 support
- Add missing PCIe PIPE clocks on Qualcomm IPQ9574
- Fix various configurations and properties in the Qualcomm SA8775P,
X1E80100 and SM7280 drivers
- Park Qualcomm SM8350 GPU RCGs on XO while disabled
- Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
- exynos-clkout: Remove usage of of_device_id table as .of_match_table,
because the driver is instantiated as MFD cell, not as standalone platform
driver. Populated .of_match_table confused people few times to convert the
code to device_get_match_data(), which broke the driver
- Mark one Samsung UFS clock as critical, because having it off stops the
system from shutdown
- Use kmemdup_array() when applicable
- Remove unused 'struct gates_data' from old sunxi driver library
- Add GPADC clock and reset for Allwinner H616
- Minor Amlogic S4 clock fixes
- DT bindings Yaml conversion of the Amlogic AXG audio controller
- Amlogic C3 clock controllers support
- Amlogic clk flag added to skip init of already enabled PLLs and avoid relocking
- Amlogic A1 DT bindings updates for system pll support
- Add missing MODULE_DESCRIPTION where necessary
- Remove obsolete clock DT binding header files
- Add Battery Backup (VBATTB) and I2C clocks, resets, and power
domains on Renesas RZ/G3S
- Add audio clocks on Renesas R-Car V4M
- Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmaZd3wRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSVwCRAAz6leVJuGDmnyNvyq+BrXOHBI89/vAI1c
ZejQLTKsXveI3fIQUTPAQ15XW1lRIPpPWRG09yZbVJ0P7WsNlfHA6KUjYiAaS9RN
zkwLSI52ZulAhdRxBycIVMnfVOnoaJs4Vvp2jLdW+cRLj9BVwC1vXSDmWENvMrh2
Om7W1r3+Utg/nO3eRVdM3+LZTfveUd6PWZnz/zp20sZLZRUeDA5DKj8fqg0dHuvZ
auZ8byeELp39rFJqE9YO5fDH+kmzXL3CAHz8s8NEDA+BBD9S4w+mvEMjHSQfQdnB
LetpZ9DPoYscnWgYS/KWCiodCIAq6ThVkkcX1lAmndPQDwPCKVOoBomNuRaNZvI8
qJnP2ZhfWMbnrc291ECbPg82RjSOtp3ZzFij2T6jwDSsBc6pmJlwSwtvjtYC7fm+
N1Ldrl2qz6BYdbqJWXBRApFdqcI8Z3aENrqpy98LJiPdGdwmcbPA2cAnEPzJENdo
ggTYXC//oVoyA6xnA1vwJQDVR0TAAu8mm3brW3uYww0T46R7HOMhtaNqIcEc1fQU
0k8mU4iW2xGQkeyR62afxDETKIe8/DMQUwoIwIZ1ogohHF+a8LmY+KnjAAmJK9LB
yHhsQUOggmRe10vVfWxDSBZRyFuPblhCYTzytoAlEUs71jLJw7PF+CrF2ZZw8fP5
OEE2/O5+XXU=
=jEjn
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This a large collection of clk driver updates and a handful of new SoC
clk driver support.
We have the usual Qualcomm clk drivers, along with clk drivers for the
Sophgo and T-Head vendors, all to support some new SoCs.
Nothing in particular stands out to me in the updates. There's the
interconnect clk driver which exposes clks as interconnects, crossing
subsystems. There's a bunch of janitorial things that are improving
drivers in general like kmemdup_array() or fixing error paths. But
overall the updates look normal to fix the description data which is
usually the stuff that's wrong and/or untested.
Core:
- Skip gate basic type KUnit tests on s390 due to lack of MMIO
emulation
New Drivers:
- AP sub-system clock controller in the T-Head TH1520
- Sophgo Sophon sg2042 clk driver
- Qualcomm SM7150 camera, display and video clk drivers
- Qualcomm QCM2290 GPU clk driver
- Qualcomm QCS8386/QCS8084 NSS clk driver
- Qualcomm SM8650 camera and video drivers
Updates:
- Add reset support to Airoha EN7581 clk driver
- Add MODULE_DESCRIPTIONs to various clk drivers
- Introduce helper logic to expose clock controllers as simple
interconnect providers
- Use the interconnect helper above on Qualcomm ipq9574
- Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on
Qualcomm X1Elite
- Improve error handling in Qualcomm kpss-xcc driver
- Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
- Export more clocks for Rockchip rk3128 peripherals
- Convert Rockchip clk drivers to use kmemdup_array()
- Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
- Make qcom_cc_really_probe() take a struct device to allow reuse in
non-platform-drivers
- Introduce prepare-only branch clock ops in the qcom clk driver to
support clocks on buses that take locks
- Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
- Support Qualcomm Huayra 2290 alpha PLL
- Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to
match HS200 support
- Add missing PCIe PIPE clocks on Qualcomm IPQ9574
- Fix various configurations and properties in the Qualcomm SA8775P,
X1E80100 and SM7280 drivers
- Park Qualcomm SM8350 GPU RCGs on XO while disabled
- Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
- exynos-clkout: Remove usage of of_device_id table as
.of_match_table, because the driver is instantiated as MFD cell,
not as standalone platform driver. Populated .of_match_table
confused people few times to convert the code to
device_get_match_data(), which broke the driver
- Mark one Samsung UFS clock as critical, because having it off stops
the system from shutdown
- Use kmemdup_array() when applicable
- Remove unused 'struct gates_data' from old sunxi driver library
- Add GPADC clock and reset for Allwinner H616
- Minor Amlogic S4 clock fixes
- DT bindings Yaml conversion of the Amlogic AXG audio controller
- Amlogic C3 clock controllers support
- Amlogic clk flag added to skip init of already enabled PLLs and
avoid relocking
- Amlogic A1 DT bindings updates for system pll support
- Add missing MODULE_DESCRIPTION where necessary
- Remove obsolete clock DT binding header files
- Add Battery Backup (VBATTB) and I2C clocks, resets, and power
domains on Renesas RZ/G3S
- Add audio clocks on Renesas R-Car V4M
- Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
clk: sunxi-ng r40: Constify struct regmap_config
clk: en7523: fix rate divider for slic and spi clocks
clk: lpc32xx: Constify struct regmap_config
clk: xilinx: Constify struct regmap_config
clk: en7523: Remove PCIe reset open drain configuration for EN7581
clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
clk: en7523: Add reset-controller support for EN7581 SoC
dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
dt-bindings: clock: sprd,sc9860-clk: convert to YAML
dt-bindings: clock: qoriq-clock: convert to yaml format
clk: qcom: Park shared RCGs upon registration
clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
...
`sun8i_r40_ccu_regmap_config` is not modified and can be declared as
const to move its data to a read-only section.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-9-7d15a0671d6f@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the GPADC required clock and reset which is used for the onboard
GPADC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240605172049.231108-3-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
drivers. And there's zero diff in the core clk framework. Instead we have new
clk drivers for STM and Sophgo, with Samsung^WGoogle in third for the diffstat
because they introduced HSI0 and HSI2 clk drivers for Google's GS101 SoC (high
speed interface things like PCIe, UFS, and MMC). Beyond those big diffs there's
the usual updates to various clk drivers for incorrect parent descriptions or
mising MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and add
actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmZGs1MRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSW2Pw/+OciG7jQzlWQD09M9qTSzygVu/0+NF8ez
ecvLnWzz3b05GSWqfeG3mm09RmaTtggwPcWx4ad5NBDxGfhn+rT72WWJt6EjA1ln
i/eNUQIlFZmiDM7Xwx6S841hcRbPz9/RRIeXtmiDkMWjsysr6MHlTkWWVMNfGkiE
9jxM5BH6N04A4664k3a4qlcZkj2KNkOLeCyzMLtm5aIwBoL3fZ+Q3sqVTgp5imt1
rzJgpGfN1QhAnd8kV2oIPtJEs9woZtRjCtTtLrTnoGf518uq25ZJx7Mz3Dx+ubUv
dtOLjjXdM+Q/ou7DM3h7HRjiZC8Mp8CprwwoxEbckBL4gBWYPyu8e6eZNBsF+3Ol
7WP3TZknDrWsUDxAcX37Euidd+hc8xtbXCQwm+QcugEee7ZXK4ElTgXwyH3FUqn2
GBI5D0+/3WyoBLqVQ7nTkMV0ps5dHrpBj6J1u/7ZfvC23/E7/5CzIxULXt1hTOcI
F1cqS78HLAc8BK3gw/63e5TtTMA4cItJD7InBB0jemfeoy03nuWzFbRUqtAStkHd
BKxmGSV3XXMdGtiN5SFy3tk7NlKeFMiVBiTzD++Vx9IL3mCdArtULu93OfUIOzXW
B/ekJKi9OHkJx3mBrbio6k4rugQDZovzWN9U2pDJtGCIaAXgYgwKuP8S9UwKLIcx
R6QarNE5Rsc=
=YoVJ
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"I'm actually surprised this time. There aren't any new Qualcomm SoC
clk drivers. And there's zero diff in the core clk framework.
Instead we have new clk drivers for STM and Sophgo, with
Samsung^WGoogle in third for the diffstat because they introduced HSI0
and HSI2 clk drivers for Google's GS101 SoC (high speed interface
things like PCIe, UFS, and MMC).
Beyond those big diffs there's the usual updates to various clk
drivers for incorrect parent descriptions or mising
MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for
the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve
issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some
boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas
R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and
add actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas
R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (118 commits)
clk: samsung: Don't register clkdev lookup for the fixed rate clocks
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: Fix SM_GPUCC_8650 dependencies
clk: qcom: Fix SC_CAMCC_8280XP dependencies
dt-bindings: clocks: stm32mp25: add access-controllers description
clock, reset: microchip: move all mpfs reset code to the reset subsystem
clk: samsung: gs101: drop unused HSI2 clock parent data
clk: rockchip: rk3568: Add PLL rate for 724 MHz
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
dt-bindings: clock: fixed: Define a preferred node name
clk: meson: s4: fix module autoloading
clk: samsung: gs101: mark some apm UASC and XIU clocks critical
clk: imx: imx8mp: Convert to platform remove callback returning void
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: bcm: dvp: Assign ->num before accessing ->hws
clk: samsung: gs101: add support for cmu_hsi2
clk: samsung: gs101: add support for cmu_hsi0
...
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded
based on the alias from of_device_id table. Clocks are considered core
components, so usually they are built-in, however these can be built and
used as modules on some generic kernel.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240410155420.224157-1-krzk@kernel.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
Use these constraints.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-4-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
these constraints.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-3-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
When the Allwinner A64's TCON0 searches the ideal rate for the connected
panel, it may happen that it requests a rate from its parent PLL-MIPI
which PLL-MIPI does not support.
This happens for example on the Olimex TERES-I laptop where TCON0
requests PLL-MIPI to change to a rate of several GHz which causes the
panel to stay blank. It also happens on the pinephone where a rate of
less than 500 MHz is requested which causes instabilities on some
phones.
Set the minimum and maximum rate of Allwinner A64's PLL-MIPI according
to the Allwinner User Manual.
Fixes: ca1170b699 ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux")
Reported-by: Diego Roversi <diegor@tiscali.it>
Closes: https://groups.google.com/g/linux-sunxi/c/Rh-Uqqa66bw
Tested-by: Diego Roversi <diegor@tiscali.it>
Cc: stable@vger.kernel.org
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-2-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The Allwinner SoC's typically have an upper and lower limit for their
clocks' rates. Up until now, support for that has been implemented
separately for each clock type.
Implement that functionality in the sunxi-ng's common part making use of
the CCF rate liming capabilities, so that it is available for all clock
types.
Suggested-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Cc: stable@vger.kernel.org
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-1-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
While PLL CPUX clock rate change when CPU is running from it works in
vast majority of cases, now and then it causes instability. This leads
to system crashes and other undefined behaviour. After a lot of testing
(30+ hours) while also doing a lot of frequency switches, we can't
observe any instability issues anymore when doing reparenting to stable
clock like 24 MHz oscillator.
Fixes: 524353ea48 ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Reported-by: Chad Wagner <wagnerch42@gmail.com>
Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/
Tested-by: Chad Wagner <wagnerch42@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20231013181712.2128037-1-jernej.skrabec@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Variable tmp_parent is being ininitialized with a value that is never
read, the initialization is redundant and can be removed. Move the
initialization and move the variable to the inner loop scope.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20231023133502.666559-1-colin.i.king@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
- Add Versa3 clk generator to support 48KHz playback/record with audio
codec on RZ/G2L SMARC EVK
- Introduce kstrdup_and_replace() and use it
* clk-versa:
clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
clk: versaclock3: Switch to use i2c_driver's probe callback
clk: Add support for versa3 clock driver
dt-bindings: clock: Add Renesas versa3 clock generator bindings
* clk-strdup:
clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()
clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()
driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace()
lib/string_helpers: Add kstrdup_and_replace() helper
* clk-amlogic: (22 commits)
dt-bindings: soc: amlogic: document System Control registers
dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
clk: meson: axg-audio: move bindings include to main driver
clk: meson: meson8b: move bindings include to main driver
clk: meson: a1: move bindings include to main driver
clk: meson: eeclk: move bindings include to main driver
clk: meson: aoclk: move bindings include to main driver
dt-bindings: clk: axg-audio-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
dt-bindings: clk: meson8b-clkc: expose all clock ids
dt-bindings: clk: g12a-aoclkc: expose all clock ids
dt-bindings: clk: g12a-clks: expose all clock ids
dt-bindings: clk: axg-clkc: expose all clock ids
dt-bindings: clk: gxbb-clkc: expose all clock ids
clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
...
* clk-allwinner:
clk: sunxi-ng: nkm: Prefer current parent rate
clk: sunxi-ng: a64: select closest rate for pll-video0
clk: sunxi-ng: div: Support finding closest rate
clk: sunxi-ng: mux: Support finding closest rate
clk: sunxi-ng: nkm: Support finding closest rate
clk: sunxi-ng: nm: Support finding closest rate
clk: sunxi-ng: Add helper function to find closest rate
clk: sunxi-ng: Add feature to find closest rate
clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
clk: sunxi-ng: nkm: Use correct parameter name for parent HW
clk: sunxi-ng: Modify mismatched function name
clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()
* clk-rockchip:
clk: rockchip: rv1126: Add PD_VO clock tree
clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
clk: rockchip: rk3568: Add PLL rate for 101MHz
Similar to ccu_mp, if the current parent rate allows getting the ideal
rate, prefer to not change the parent clock's rate.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-11-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Selecting the closest rate for pll-video0 instead of the closest rate
that is less than the requested rate has no downside for this clock,
while allowing for selecting a more suitable rate, e.g. for the
connected panels.
Furthermore, the algorithm that sets an NKM clock's parent benefits from
the closest rate. Without it, the NKM clock's rate might drift away from
the requested rate in the multiple successive calls to
ccu_nkm_determine_rate that the clk framework performs when setting a
clock rate.
Therefore, configure pll-video0 and, in consequence, all of its
descendents to select the closest rate.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-10-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Add initalization macros for divisor clocks with mux
(SUNXI_CCU_M_WITH_MUX) to support finding the closest rate. This clock
type requires the appropriate flags to be set in the .common structure
(for the mux part of the clock) and the .div part.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-9-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
When finding the best rate for a mux clock, consider rates that are
higher than the requested rate when CCU_FEATURE_ROUND_CLOSEST is used.
Furthermore, introduce an initialization macro that sets this flag.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-8-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
When finding the best rate for a NKM clock, consider rates that are
higher than the requested rate, if the CCU_FEATURE_CLOSEST_RATE flag is
set by using the helper function ccu_is_better_rate().
Accommodate ccu_mux_helper_determine_rate to this change.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-7-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Use the helper function ccu_is_better_rate() to determine the rate that
is closest to the requested rate, thereby supporting rates that are
higher than the requested rate if the clock uses the
CCU_FEATURE_CLOSEST_RATE.
Add the macro SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST which
sets CCU_FEATURE_CLOSEST_RATE.
To avoid code duplication, add the macros
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT that allows selecting
arbitrary features and use it in the original
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX as well as the newly introduced
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST macros.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-6-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The default behaviour of clocks in the sunxi-ng driver is to select a
clock rate that is closest to but less than the requested rate.
Add the ccu_is_better_rate() helper function that - depending on the
fact if thc CCU_FEATURE_CLOSEST_RATE flag is set - decides if a rate is
closer than another rate.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-5-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The default behaviour of clocks in the sunxi-ng driver is to select a
clock rate that is closest to but less than the requested rate.
Add the CCU_FEATURE_CLOSEST_RATE flag, which can be used to allow clocks
to find the closest rate instead.
Acked-by: Maxime Ripard <mripard@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-4-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The nkm clock now supports setting the parent's rate. Utilize this
option to find the optimal rate for pll-mipi.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-3-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
In case the CLK_SET_RATE_PARENT flag is set, consider using a different
parent rate when determining a new rate.
To find the best match for the requested rate, perform the following
steps for each NKM combination:
- calculate the optimal parent rate,
- find the best parent rate that the parent clock actually supports
- use that parent rate to calculate the effective rate.
In case the clk does not support setting the parent rate, use the same
algorithm as before.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-2-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ccu_nkm_round_rate() takes a clk_hw as parameter "hw". Since "hw" is the
nkm clock's parent clk_hw, not the clk_hw of the nkm clock itself,
change the parameter name to "parent_hw" to make it more clear what
we're dealing with.
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-1-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung
Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org
Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
however MIPI DSI output only seems to work when PLL_MIPI is selected and
thus the choice must be hardcoded in.
Currently, this driver can't propagate rate change from N-K-M clocks
(such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
in setting of the TCON0 data clock rate, limiting the precision with
which a target pixel clock can be matched.
For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
can deviate up to 8% off target.
Signed-off-by: Roman Beranek <me@crly.cz>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20230505052110.67514-2-me@crly.cz
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The D1 CCU contains gates and resets for two CAN buses. While the CAN
bus controllers are only documented for the T113 SoC, the CCU is the
same across all SoC variants.
Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221231231429.18357-7-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU.
In that case, the CPUs are driven from the 'cpux' clock, so it needs
to be marked as critical, since there is no consumer when DVFS is
disabled. This matches the drivers for other SoCs, and the "riscv"
clock in this driver.
Signed-off-by: András Szemző <szemzo.andras@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221231231429.18357-5-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Allwinner released some 32-bit ARM (sun8i) SoCs which use the same CCU
as D1. Allow them to reuse the driver.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221231231429.18357-4-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Do not duplicate the same expression on the `default` line, so the two
lines do not need to be kept in sync. Drivers stay disabled under
COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU.
Three drivers had no conditions.
- SUN6I_RTC_CCU and SUN8I_DE2_CCU are used on current hardware
regardless of CPU architecture.
- SUN8I_R_CCU is only used on pre-H6 SoCs, which means no RISCV SoCs.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221231231429.18357-3-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
SUNXI_CCU already depends on ARCH_SUNXI, so adding the dependency to
individual SoC drivers is redundant. Drivers stay disabled under
COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221231231429.18357-2-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The ccu_*_find_best() functions already compute a best_rate at the same
time as the other factors. Return this value so the caller does not need
to duplicate the computation.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20221231173055.42384-1-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The DRAM controller clock is only allowed to change frequency while the
DRAM chips are in self-refresh. To support this, changes to the CLK_DRAM
mux and divider have no effect until acknowledged by the memory dynamic
frequency scaling (MDFS) hardware inside the DRAM controller. (There is
a SDRCLK_UPD bit in DRAM_CFG_REG which should serve a similar purpose,
but this bit actually does nothing.)
However, the MDFS hardware in H3 appears to be broken. Triggering a
frequency change using the procedure from similar SoCs (A64/H5) hangs
the hardware. Additionally, the vendor BSP specifically avoids using the
MDFS hardware on H3, instead performing all DRAM PHY parameter updates
and resets in software.
Thus, it is effectively impossible to change the CLK_DRAM mux/divider,
so those features should not be modeled. Add CLK_SET_RATE_PARENT so
frequency changes apply to PLL_DDR instead.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221229042230.24532-1-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Use '-' to separate the function name and its description.
Use '%' on constants in kernel-doc notation.
Use the kernel-doc Return: format for function return values.
Fixes this warning:
ccu_mmc_timing.c:21: warning: No description found for return value of 'sunxi_ccu_set_mmc_timing_mode'
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Yang Li <yang.lee@linux.alibaba.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Samuel Holland <samuel@sholland.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@lists.linux.dev
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20221122184844.6794-1-rdunlap@infradead.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
For some reason the mod clock for the Allwinner F1C100s CIR (infrared
receiver) peripheral was not modeled in the CCU driver.
Add the clock description to the list, and wire it up in the clock list.
By assigning a new clock ID at the end, it extends the number of clocks.
This allows to use the CIR peripheral on any F1C100s series board.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-5-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Rename the header guard of ccu-sun8i-v3s.h from _CCU_SUN8I_H3_H_ to
_CCU_SUN8I_V3S_H_ what corresponding with the file name.
Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Wei Li <liwei391@huawei.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221108094335.3597008-1-liwei391@huawei.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
late breaking reports that a patch series to rework clk rate range
support broke boot on some devices, so I've left that branch out of this
PR. Hopefully we can get to that next week, or punt on it and let it
bake another cycle. That means we don't really have any changes to the
core framework this time around besides a few typo fixes. Instead this
is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm drivers
to use clk_parent_data. After that we have MediaTek drivers getting some
much needed updates, in particular to support GPU DVFS. There are also
quite a few Samsung clk driver patches, but that's mostly because there
was a maintainer change and so last release we missed some of those
patches.
Overall things look normal, but I'm slowly reviewing core framework code
nowadays and that shows given the rate range patches had to be yanked
last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper, code
style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention
issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was
added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmM/trwRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSUEoA/+LiftbrF8Xtu7lGdxRjqLzRftUmHaUQWO
d0cadtzMsgxzFJsxp99IiJBVJoaYCBOGlnZDx8p/JGv+mmdhl5+yHgKQbR8nEmTk
5A+bdA1okOdm8SPBPMcLvuMjsgmx+DHkuxvnC2hT8ZGfQDoa+6PnObpP30LJkHT0
oVY8g8ScEuHI5eJcNz3UgxAetKeJd+WRQPxKCrjsOeyhWuNAJ7wdTVQjjzH49X4C
RS3fjeHvhr2VZm23IgildY++a6hPO72gtBjEpDRoFwnmWAVqUtxiwptoJJNkC5kB
toD/ndQHOLh/XOJFKgksS20L4JHtSp5F3Ma8sIuOjAXmDCyqMdTQhydnl5Pyrow+
ct8BMUGkx0Sw8pXBJYINtHpwTtIxvLu/sBNqBb/lRCWd8byrPlUnKvF/COcoxp27
miZTwJI28fHU5a2K/46iWZCI5YUvVcnBSz8WbEWWvOltIT8S0JvZozA3KuRm5vys
/k2HaQwO2I0QWQzPjfg6SRlTTWH6p+Hc47fSg7LSM6Scsb7ZraajTM2QOvgn7Mgp
m/136q7jr9mvuLqqy1fBY3F2hDZYNSJX+UfmIFcpCyxvht0GVFN9YCc+Ibgyl2vQ
P3b9LXV2OqhtDJg6ds7v8aPgAGUwUFO8GTPBG1cuom7z5u/kdIpjKaFAyr8wWSuJ
wqPIFevggsA=
=9jI+
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have some late breaking reports that a patch series to rework clk
rate range support broke boot on some devices, so I've left that
branch out of this. Hopefully we can get to that next week, or punt on
it and let it bake another cycle. That means we don't really have any
changes to the core framework this time around besides a few typo
fixes. Instead this is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm
drivers to use clk_parent_data. After that we have MediaTek drivers
getting some much needed updates, in particular to support GPU DVFS.
There are also quite a few Samsung clk driver patches, but that's
mostly because there was a maintainer change and so last release we
missed some of those patches.
Overall things look normal, but I'm slowly reviewing core framework
code nowadays and that shows given the rate range patches had to be
yanked last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on
RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to
dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on
MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper,
code style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
he already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
retention issues during suspend of USB on Qualcomm sc7180/sc7280
and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
was added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
clk: qcom: gcc-sm6375: Ensure unsigned long type
clk: qcom: gcc-sm6375: Remove unused variables
clk: qcom: kpss-xcc: convert to parent data API
clk: introduce (devm_)hw_register_mux_parent_data_table API
clk: allow building lan966x as a module
clk: clk-xgene: simplify if-if to if-else
clk: ast2600: BCLK comes from EPLL
clk: clocking-wizard: Depend on HAS_IOMEM
clk: clocking-wizard: Use dev_err_probe() helper
clk: nxp: fix typo in comment
clk: pxa: add a check for the return value of kzalloc()
clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
dt-bindings: clock: vc5: Add 5P49V6975
clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
clk: Renesas versaclock7 ccf device driver
dt-bindings: Renesas versaclock7 device tree bindings
clk: ti: Balance of_node_get() calls for of_find_node_by_name()
clk: imx: scu: fix memleak on platform_device_add() fails
clk: vc5: Use regmap_{set,clear}_bits() where appropriate
...
In commit 4167ac8a65 ("clk: sunxi-ng: sun50i: h6: Modify GPU clock
configuration to support DFS") divider M0 was forced to be 1 in order to
support DFS. However, that left N as it is, at high value of 36. On
boards without devfreq enabled (all of them in kernel 6.0), this
effectively sets GPU frequency to 864 MHz. This is about 100 MHz above
maximum supported frequency.
In order to fix this, let's set N to 18 (register value 17). That way
default frequency of 432 MHz is preserved.
Fixes: 4167ac8a65 ("clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220928200122.3963509-1-jernej.skrabec@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dev_err() can be replace with dev_err_probe() which will check if error
code is -EPROBE_DEFER.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220827094151.3323450-3-yangyingliang@huawei.com
dev_err() can be replace with dev_err_probe() which will check if error
code is -EPROBE_DEFER.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220827094151.3323450-2-yangyingliang@huawei.com
dev_err() can be replace with dev_err_probe() which will check if error
code is -EPROBE_DEFER.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220827094151.3323450-1-yangyingliang@huawei.com
Set the min/max rates for audio and video PLLs to keep them from going
outside their documented stable ranges. Use the most restrictive of the
"stable" and "actual" frequencies listed in the manual.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220812080050.59850-1-samuel@sholland.org
Using simple bash script it was discovered that not all CCU registers
can be safely used for DFS, e.g.:
while true
do
devmem 0x3001030 4 0xb0003e02
devmem 0x3001030 4 0xb0001e02
done
Script above changes the GPU_PLL multiplier register value. While the
script is running, the user should interact with the user interface.
Using this method the following results were obtained:
| Register | Name | Bits | Values | Result |
| -- | -- | -- | -- | -- |
| 0x3001030 | GPU_PLL.MULT | 15..8 | 20-62 | OK |
| 0x3001030 | GPU_PLL.INDIV | 1 | 0-1 | OK |
| 0x3001030 | GPU_PLL.OUTDIV | 0 | 0-1 | FAIL |
| 0x3001670 | GPU_CLK.DIV | 3..0 | ANY | FAIL |
DVFS started to work seamlessly once dividers which caused the
glitches were set to fixed values.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220705075226.359475-1-r.stratiienko@gmail.com
