Fix seveal odd-looking places in SM8550's dispcc driver:
- duplicate entries in disp_cc_parent_map_4 and disp_cc_parent_map_5
- using &disp_cc_mdss_dptx0_link_div_clk_src as a source for
disp_cc_mdss_dptx1_usb_router_link_intf_clk
The SM8650 driver has been used as a reference.
Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-1-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add support for the camera clock controller for camera clients
to be able to request for camcc clocks on SM8150 platform.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-8-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
value is greater than 0.5, the L value needs to be adjusted accordingly.
Thus update the logic to handle the signed alpha val.
Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the
PLL is disabled. However, if the PLL is disabled then LOCK_DET will
never assert and we'll return an error. There is no reason to poll
LOCK_DET if the PLL is already disabled, so skip polling in this case.
Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240731062916.2680823-4-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate
API. The shift value is not same for different types of plls and
should be taken from the pll's .post_div_shift member.
Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240731062916.2680823-3-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
Cc: stable@vger.kernel.org
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The USB multiport controller needs a few additional resets, add these to
the driver.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-2-a7dc4265b553@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the CLK_IGNORE_UNUSED flag to the vp-axi clock (CLK_VP_AXI) to avoid
depending on clk_ignore_unused in the cmdline. Without this fix, the
emmc-sdio clock (CLK_EMMC_SDIO) fails to work after vp-axi is disabled.
Signed-off-by: Drew Fustini <drew@pdp7.com>
Link: https://lore.kernel.org/r/20240731061439.3807172-1-drew@pdp7.com
Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add TMU PCLK clock in CMU_PERI unit. It acts simultaneously as an
interface clock (to access TMU registers) and an operating clock which
makes TMU IP-core functional.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240723163311.28654-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The default PLL2/3/4/6 multiplier and divider configurations are no
longer used after the conversion to fixed or variable fractional PLL
clock types.
Note that the default configurations are still documented in the
comments above the individual rcar_gen4_cpg_pll_config instances.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
Currently, all PLLs are modelled as fixed divider clocks, based on the
state of the mode pins. However, the boot loader stack may have changed
the actual PLL configuration from the default, leading to incorrect
clock frequencies.
Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4,
and PLL6 as variable fractional PLLs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/3beac7c44534ed153ce7cea5c31f4b0bb7b16ab0.1721648548.git.geert+renesas@glider.be
Currently, all PLLs but PLL2 are modelled as fixed divider clocks, based
on the state of the mode pins. However, the boot loader stack may have
changed the actual PLL configuration from the default, leading to
incorrect clock frequencies.
Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4,
and PLL6 as variable fractional PLLs.
Reformat nearby lines to retain a consistent layout.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/b98523ed08de7386944c5ae860eae107dc28be3e.1721648548.git.geert+renesas@glider.be
Currently, all PLLs are modelled as fixed divider clocks, based on the
state of the mode pins. However, the boot loader stack may have changed
the actual PLL configuration from the default, leading to incorrect
clock frequencies.
Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, and
PLL6 as variable fractional PLLs. Note that the R-Car Gen4 clock driver
does not support variable 9.24 PLLs yet, so the driver will downgrade
them to fixed fractional PLLs, too.
Reformat nearby lines to retain a consistent layout.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8544571f507e00ed6fc61617d27c9e19de5e9d11.1721648548.git.geert+renesas@glider.be
The custom clock driver that models the PLL clocks on R-Car Gen4
supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M.
R-Car S4-8 uses integer and fractional multiplication fields that are
one bit larger resp. smaller, and a slightly different formula.
Extend the existing support to fractional 9.24 PLL, and introduce new
clock types and helper macros to describe these PLLs.
Note that there is no use case for variable fractional 9.24 PLLs yet, as
the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode.
Hence the PLL is always modeled as a fixed PLL, regardless of the
description,
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/5684eda1260435c8eceabc274e0b18cb280a6341.1721648548.git.geert+renesas@glider.be
The custom clock driver that models PLL clocks on R-Car Gen4 supports
variable clocks, while PLL1 uses a similar control register layout, but
is read-only.
Extend the existing support to fixed clocks and PLL1, and introduce a
new clock type and helper macro to describe a fixed PLL.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/841fbb63d472c357b3ce291a5991db3b847f96d8.1721648548.git.geert+renesas@glider.be
The custom clock driver that models PLL clocks on R-Car Gen4 supports
PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same
control register layout.
Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new
clock type and helper macro to describe these PLLs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be
R-Car Gen4 PLLs support fractional multiplication, which can improve
accuracy when configuring a specific frequency.
Add support for fractional multiplication to the custom clock driver
for PLLs, which is currently used only for PLL2 on R-Car V4H.
While at it, add the missing blank line after the function.
Note that Fractional Multiplication is not enabled by the driver,
but used only if the boot loaded enabled it before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/1a58ebef6f54460f49fb81ba9bbf288164de2646.1721648548.git.geert+renesas@glider.be
Improve readability by using the FIELD_GET() helper instead of
open-coding the same operation, and by adding field definitions to get
rid of hardcoded values.
While at it, move register definitions that are only used inside the
rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file.
Add a "CPG_" prefix to SD0CKCR1. Add comments where appropriate.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/fb19ad829738f02effa340fa04c178a162d41202.1721648548.git.geert+renesas@glider.be
The custom clock driver that models the PLL clocks on R-Car Gen4 assumes
the integer and fractional[*] multiplication field sizes as used on
R-Car V4H and V4M, representing a fractional 8.25 number.
Rename the related definitions, functions, and structures to clarify
this, and to prepare for the advent of support for the different field
sizes on R-Car S4-8.
[*] The fractional part is not yet supported.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/2ce9f9c75bfb6312129d416672f9691bbd11c0e7.1721648548.git.geert+renesas@glider.be
Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and
`base` parameters in various clock registration functions. These values
are now accessed directly from the `priv` structure.
While at it, drop masking of parent clocks with 0xffff as nothing is ever
stored in the high bits.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240715103555.507767-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
We are using devres APIs for divider, mux and pll5 clocks so for
consistency use the devres APIs for module, fixed factor and PLL clocks.
While at it switched to clk_hw_register() instead of clk_register()
as this has been marked as deprecated interface.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240715103555.507767-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
r8a779h0_core_clks[], r8a779h0_mod_clks[], and cpg_pll_configs[] are
only used during initialization. Hence make them __initconst, so they
will be freed later.
Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/35bbcfb914ddb377fa77e3425e4e7e232c7c2cf9.1720794214.git.geert+renesas@glider.be
cpg_pll_configs[] is only used during initialization. Hence make it
__initconst, so it will be freed later.
Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/ea806a096d47382f4f560b20f1038f03b4e44e0e.1720794214.git.geert+renesas@glider.be
cpg_pll_configs[] is only used during initialization. Hence make it
__initconst, so it will be freed later.
Fixes: 24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/2261fc8291099445e1b319812dfd4f79c90296d2.1720794214.git.geert+renesas@glider.be
cpg_pll_configs[] is only used during initialization. Hence make it
__initconst, so it will be freed later.
Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/a9819625329b188c298481402e1c55ac46093518.1720794214.git.geert+renesas@glider.be
Add the PCIe module clock, which is used by the PCIe module on the
Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240704061720.1444755-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The use of the __free function allows the cleanup to be based on scope
instead of on another function called later. This makes the cleanup
automatic and less susceptible to errors later.
This code was compiled without errors or warnings.
Signed-off-by: David Hunter <david.hunter.linux@gmail.com>
Link: https://lore.kernel.org/r/20240720152447.311442-1-david.hunter.linux@gmail.com
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Now that all clock controllers have been migrated to the new
mtk_register_reset_controller_with_dev() function, the one taking
struct device node is now unused: remove it.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240718082528.220750-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
device_node_to_regmap() can return different errors, and it's better
practice to pass them to callers.
Clean up the hardcoded -EINVAL and use PTR_ERR(regmap) instead.
Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20240717115919.975474-1-fshao@chromium.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Test that clks registered with 'struct clk_parent_data' work as
intended and can find their parents.
Cc: Christian Marangi <ansuelsmth@gmail.com>
Cc: Brendan Higgins <brendan.higgins@linux.dev>
Reviewed-by: David Gow <davidgow@google.com>
Cc: Rae Moar <rmoar@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20240718210513.3801024-9-sboyd@kernel.org
Test that the fixed rate basic type clk works as intended.
Cc: Brendan Higgins <brendan.higgins@linux.dev>
Cc: David Gow <davidgow@google.com>
Cc: Rae Moar <rmoar@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20240718210513.3801024-8-sboyd@kernel.org
Unit tests are more ergonomic and simpler to understand if they don't
have to hoist a bunch of code into the test harness init and exit
functions. Add some test managed wrappers for the clk APIs so that clk
unit tests can write more code in the actual test and less code in the
harness.
Only add APIs that are used for now. More wrappers can be added in the
future as necessary.
Cc: Brendan Higgins <brendan.higgins@linux.dev>
Cc: David Gow <davidgow@google.com>
Cc: Rae Moar <rmoar@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20240718210513.3801024-7-sboyd@kernel.org
Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
parented by the hdmiphy clk and it is expected that the DCLK_VOP and
hdmiphy clk rate are kept in sync.
Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
on RK3328, to make full use of all possible supported display modes.
Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240615170417.3134517-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Symbols exported by the Amlogic clock modules are only meant to be used by
Amlogic clock controller drivers. Using a dedicated symbols namespace make
that clear and help clean the global namespace of symbols other modules do
no need.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240719094228.3985595-1-jbrunet@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The register region of axg-audio tends to grow with the addition of
new supported SoC. Mapping slightly more has not been causing problem
so far but it is not viable to continue like this long term.
Setup the max register based on what is necessary on the related SoC.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240719093934.3985139-3-jbrunet@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of PCIe controllers from suspend.
So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.
Cc: stable@vger.kernel.org # 5.17
Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240722105733.13040-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of PCIe controllers from suspend.
So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.
Cc: stable@vger.kernel.org # 5.7
Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240719134238.312191-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
'struct freq_tbl' are not modified in these drivers.
Constifying this structure moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig, as an example:
Before:
======
text data bss dec hex filename
7595 43696 0 51291 c85b drivers/clk/qcom/mmcc-apq8084.o
After:
=====
text data bss dec hex filename
9867 41424 0 51291 c85b drivers/clk/qcom/mmcc-apq8084.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/e8aee66fa83a4e65f7e855eb8bdbc91275d6994b.1720962107.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
- Treewide conversion of of_property_for_each_u32() to drop internal
arguments making struct property opaque
- Add binding for Amlogic A4 SoC watchdog
- Fix constraints for AD7192 'single-channel' property
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmaj8ncACgkQ+vtdtY28
YcMwZRAAh618Xfw+J8pxv62PMw11r0hgMNYoHPYDMt47D7g9Wwa71xdR6OpfIpf+
EyHUXrnXJT6f5sm8mVe9Gsni0MZfgdkwchxlCQej0rJKchdLdAFNXbg4GbhF+0Ht
tA3Y6bPB9FYKHExd87flnt4AO3ypF+1ihjSAAoy4EyEZUfyKgQVPyebDGwlPYlkH
dmhF+q9d94LVw3lj/C7htWGELProogsU3i498ey7m/w8jwiJav2DVJ0cRuld/aPG
7VwGQhJzdndlH1MPcl9slzIPadUrZ0S3/7V4c9cC0E22XpHJzp4RSdGmzsXJ7adp
Q+OlQYiyZLLhEA/alVO/j5SJtfxt+T6+lrpbbu1wcJMFoukXusvL+0KbxxbExEn0
/3MrZuxEq3F+jcKtMR/1PFcO7o1uEzzyTZcdufV3siABjZqmG4AFzBhHWP4Xh2Uw
6hs7R/Ktf2lmacCK9fawfJF6Qq4RtFIakUuI6S3Q3oHHTRw6kr1Lsw+Wko/K20mO
BEdfhocxEk5vf/kGxcBfM+GTybhagbBh0GxYB/Lm8vATfLHzhunipbc0ZwozDfPu
IWiY+Nv+hGeGhfvSfNFUcsknF+QwtSjGis7hQjHkJc/siahaXJVAaf+tvtL1xm/p
0CGPIJFZgzkcbjCT3iPVaJjfyRlMe9l7HJ6XiBSrMpiFpZPTgT8=
=Nn/d
-----END PGP SIGNATURE-----
Merge tag 'devicetree-fixes-for-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull more devicetree updates from Rob Herring:
"Most of this is a treewide change to of_property_for_each_u32() which
was small enough to do in one go before rc1 and avoids the need to
create of_property_for_each_u32_some_new_name().
- Treewide conversion of of_property_for_each_u32() to drop internal
arguments making struct property opaque
- Add binding for Amlogic A4 SoC watchdog
- Fix constraints for AD7192 'single-channel' property"
* tag 'devicetree-fixes-for-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dt-bindings: iio: adc: ad7192: Fix 'single-channel' constraints
of: remove internal arguments from of_property_for_each_u32()
dt-bindings: watchdog: add support for Amlogic A4 SoCs
some SoCs.
- Initialize struct clk_init_data in the TI da8xx-cfgchip driver so
that stack contents aren't used for things like clk flags leading to
unexpected behavior
- Don't leak stack contents in a debug print in the new Sophgo clk
driver
- Disable the new T-Head clk driver on 32-bit targets to fix the build
due to a division
- Fix Samsung Exynos4 fin_pll wreckage from the clkdev rework done last
cycle by using a struct clk_hw directly instead of a struct clk
consumer
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmaj7w8RHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSVJbRAAkyHgShvwM/pnjVKAD6F5p6gUd3S7RnS8
gaV77KUthhWzNE8TXneGA20RUNUYgRbIWSC3YWA1V8p4sb8d8SGMPDxzcFuEa4eq
qLBvb3lNcynyhpfMErRpVvF5EZxqdJkGJdSgF+QzYZLJL28Bff3eKwNM7K6cgl41
W4Je2E4dmifqqeOwWl/1YiAh/GN03C470q4DP9Jekeqn5nZie4ZNttD72XIhywSS
i11tWQ5E4JBcGkg0beCwwsiDo/Snpzt1JOtCuargbn3IupAiUcZJayycE8sUFJ/U
Ath/ZJerBEPYzmcHfwg9JKnaDFPucaOkszcAxysZvNYerjvD/jZG64C1nnl4KURt
DUlYNxjzbzQ3Byr1182D4tFOOUi0XzR5SG2lv/6syv6nDifIuzjz5AVIQDHweJb1
49j40HdzpzdBQjicepIf+g96Ej+5qVaIoHgBZPMxsEli95VfITTzb+K+Uv4UjkxG
o8BYm3IJKUvF1E3tnjswVjG2Lm9xMfm674WwJs7uUKHYy7Y+b8g8a9yuSz1rhL0d
0jZ1yyBIhqJe9UVGB3YUOOxu//W/r9do1bsAj0rCGR5m/D0XPNj63NuOBQUzdGZ8
c+xIL2GYfGkcprkEVznU29AOoxnl47bzwW1C2Y4G7w2kuh3lNXq+9N2Mpe4+juE4
C5M6xdxmeCI=
=tIM4
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few clk driver fixes for the merge window to fix the build and boot
on some SoCs.
- Initialize struct clk_init_data in the TI da8xx-cfgchip driver so
that stack contents aren't used for things like clk flags leading
to unexpected behavior
- Don't leak stack contents in a debug print in the new Sophgo clk
driver
- Disable the new T-Head clk driver on 32-bit targets to fix the
build due to a division
- Fix Samsung Exynos4 fin_pll wreckage from the clkdev rework done
last cycle by using a struct clk_hw directly instead of a struct
clk consumer"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: samsung: fix getting Exynos4 fin_pll rate from external clocks
clk: T-Head: Disable on 32-bit Targets
clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug output
clk: davinci: da8xx-cfgchip: Initialize clk_init_data before use
