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02fb4f0084
Flexible-array member `hws` in `struct clk_hw_onecell_data` is annotated
with the `counted_by()` attribute. This means that when memory is
allocated for this array, the _counter_, which in this case is member
`num` in the flexible structure, should be set to the maximum number of
elements the flexible array can contain, or fewer.
In this case, the total number of elements for the flexible array is
determined by variable `clks_num` when allocating heap space via
`devm_kzalloc()`, as shown below:
289 struct loongson2_clk_provider *clp;
...
296 for (p = data; p->name; p++)
297 clks_num++;
298
299 clp = devm_kzalloc(dev, struct_size(clp, clk_data.hws, clks_num),
300 GFP_KERNEL);
So, `clp->clk_data.num` should be set to `clks_num` or less, and not
exceed `clks_num`, as is currently the case. Otherwise, if data is
written into `clp->clk_data.hws[clks_num]`, the instrumentation
provided by the compiler won't detect the overflow, leading to a
memory corruption bug at runtime.
Fix this issue by setting `clp->clk_data.num` to `clks_num`.
Fixes: 9796ec0bd0 ("clk: clk-loongson2: Refactor driver for adding new platforms")
Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/ZzaN5MpmMr0hwHw9@kspp
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
376 lines
12 KiB
C
376 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Author: Yinbo Zhu <zhuyinbo@loongson.cn>
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <dt-bindings/clock/loongson,ls2k-clk.h>
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static const struct clk_parent_data pdata[] = {
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{ .fw_name = "ref_100m", },
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};
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enum loongson2_clk_type {
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CLK_TYPE_PLL,
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CLK_TYPE_SCALE,
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CLK_TYPE_DIVIDER,
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CLK_TYPE_GATE,
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CLK_TYPE_FIXED,
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CLK_TYPE_NONE,
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};
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struct loongson2_clk_provider {
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void __iomem *base;
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struct device *dev;
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spinlock_t clk_lock; /* protect access to DIV registers */
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/* Must be last --ends in a flexible-array member. */
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struct clk_hw_onecell_data clk_data;
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};
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struct loongson2_clk_data {
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struct clk_hw hw;
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void __iomem *reg;
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u8 div_shift;
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u8 div_width;
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u8 mult_shift;
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u8 mult_width;
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};
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struct loongson2_clk_board_info {
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u8 id;
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enum loongson2_clk_type type;
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const char *name;
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const char *parent_name;
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unsigned long fixed_rate;
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u8 reg_offset;
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u8 div_shift;
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u8 div_width;
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u8 mult_shift;
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u8 mult_width;
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u8 bit_idx;
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};
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#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_DIVIDER, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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}
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#define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \
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_dshift, _dwidth) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_PLL, \
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.name = _name, \
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.parent_name = NULL, \
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.reg_offset = _offset, \
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.mult_shift = _mshift, \
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.mult_width = _mwidth, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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}
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#define CLK_SCALE(_id, _name, _pname, _offset, \
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_dshift, _dwidth) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_SCALE, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.div_shift = _dshift, \
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.div_width = _dwidth, \
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}
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#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_GATE, \
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.name = _name, \
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.parent_name = _pname, \
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.reg_offset = _offset, \
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.bit_idx = _bidx, \
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}
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#define CLK_FIXED(_id, _name, _pname, _rate) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_FIXED, \
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.name = _name, \
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.parent_name = _pname, \
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.fixed_rate = _rate, \
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}
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static const struct loongson2_clk_board_info ls2k0500_clks[] = {
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CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
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CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
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CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0, 24, 6),
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CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x8, 24, 6),
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CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0xc, 8, 6),
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CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_soc", 0x10, 24, 6),
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CLK_DIV(LOONGSON2_DC_CLK, "clk_sb", "pll_soc", 0x14, 0, 6),
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CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_soc", 0x14, 8, 6),
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CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x18, 24, 6),
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CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x20, 24, 6),
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CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", "clk_sb", 0x28, 8, 3),
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CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_sb", 0x28, 12, 3),
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CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_sb", 0x28, 16, 3),
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CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_sb", 0x28, 20, 3),
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{ /* Sentinel */ },
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};
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static const struct loongson2_clk_board_info ls2k1000_clks[] = {
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CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_DC_PLL, "pll_dc", 0x20, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
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CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 32, 10, 26, 6),
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CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0x8, 0, 6),
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CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x18, 0, 6),
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CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_ddr", 0x18, 22, 6),
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/*
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* The hda clk divisor in the upper 32bits and the clk-prodiver
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* layer code doesn't support 64bit io operation thus a conversion
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* is required that subtract shift by 32 and add 4byte to the hda
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* address
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*/
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CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0x22, 12, 7),
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CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "pll_dc", 0x28, 0, 6),
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CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_dc", 0x28, 22, 6),
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CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x38, 0, 6),
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CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x38, 0, 6),
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CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 8, 3),
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CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_gmac", 0x50, 12, 3),
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CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_gmac", 0x50, 16, 3),
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CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_gmac", 0x50, 20, 3),
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{ /* Sentinel */ },
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};
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static const struct loongson2_clk_board_info ls2k2000_clks[] = {
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CLK_PLL(LOONGSON2_DC_PLL, "pll_0", 0, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_DDR_PLL, "pll_1", 0x10, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_NODE_PLL, "pll_2", 0x20, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
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CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 21, 9, 32, 6),
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CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
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CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
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CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
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CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
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CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
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CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
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CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
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CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
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CLK_GATE(LOONGSON2_EMMC_GATE, "emmc_gate", "pll_2", 0x20, 42),
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CLK_GATE(LOONGSON2_PIX0_GATE, "pix0_gate", "pll_pix0", 0x30, 40),
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CLK_GATE(LOONGSON2_PIX1_GATE, "pix1_gate", "pll_pix1", 0x40, 40),
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CLK_DIV(LOONGSON2_OUT0_CLK, "clk_out0", "out0_gate", 0, 0, 6),
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CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "gmac_gate", 0, 7, 6),
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CLK_DIV(LOONGSON2_RIO_CLK, "clk_rio", "rio_gate", 0, 14, 6),
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CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "dc_gate", 0x10, 0, 6),
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CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "gpu_gate", 0x10, 7, 6),
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CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "ddr_gate", 0x10, 14, 6),
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CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "hda_gate", 0x20, 0, 6),
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CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "node_gate", 0x20, 7, 6),
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CLK_DIV(LOONGSON2_EMMC_CLK, "clk_emmc", "emmc_gate", 0x20, 14, 6),
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CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x30, 0, 6),
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CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x40, 0, 6),
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CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_out0", 0x50, 12, 3),
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CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_out0", 0x50, 16, 3),
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CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_node", 0x50, 20, 3),
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CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 23, 3),
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CLK_SCALE(LOONGSON2_DES_CLK, "clk_des", "clk_node", 0x50, 40, 3),
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CLK_SCALE(LOONGSON2_I2S_CLK, "clk_i2s", "clk_node", 0x50, 44, 3),
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CLK_FIXED(LOONGSON2_MISC_CLK, "clk_misc", NULL, 50000000),
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{ /* Sentinel */ },
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};
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static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct loongson2_clk_data, hw);
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}
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static inline unsigned long loongson2_rate_part(u64 val, u8 shift, u8 width)
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{
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return (val & GENMASK(shift + width - 1, shift)) >> shift;
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}
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static unsigned long loongson2_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u64 val, mult, div;
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struct loongson2_clk_data *clk = to_loongson2_clk(hw);
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val = readq(clk->reg);
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mult = loongson2_rate_part(val, clk->mult_shift, clk->mult_width);
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div = loongson2_rate_part(val, clk->div_shift, clk->div_width);
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return div_u64((u64)parent_rate * mult, div);
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}
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static const struct clk_ops loongson2_pll_recalc_ops = {
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.recalc_rate = loongson2_pll_recalc_rate,
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};
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static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u64 val, mult;
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struct loongson2_clk_data *clk = to_loongson2_clk(hw);
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val = readq(clk->reg);
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mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
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return div_u64((u64)parent_rate * mult, 8);
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}
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static const struct clk_ops loongson2_freqscale_recalc_ops = {
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.recalc_rate = loongson2_freqscale_recalc_rate,
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};
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static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
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const struct loongson2_clk_board_info *cld,
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const struct clk_ops *ops)
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{
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int ret;
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struct clk_hw *hw;
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struct loongson2_clk_data *clk;
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struct clk_init_data init = { };
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clk = devm_kzalloc(clp->dev, sizeof(*clk), GFP_KERNEL);
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if (!clk)
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return ERR_PTR(-ENOMEM);
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init.name = cld->name;
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init.ops = ops;
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init.flags = 0;
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init.num_parents = 1;
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if (!cld->parent_name)
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init.parent_data = pdata;
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else
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init.parent_names = &cld->parent_name;
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clk->reg = clp->base + cld->reg_offset;
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clk->div_shift = cld->div_shift;
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clk->div_width = cld->div_width;
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clk->mult_shift = cld->mult_shift;
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clk->mult_width = cld->mult_width;
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clk->hw.init = &init;
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hw = &clk->hw;
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ret = devm_clk_hw_register(clp->dev, hw);
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if (ret)
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clk = ERR_PTR(ret);
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return hw;
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}
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static int loongson2_clk_probe(struct platform_device *pdev)
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{
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int i, clks_num = 0;
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struct clk_hw *hw;
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struct device *dev = &pdev->dev;
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struct loongson2_clk_provider *clp;
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const struct loongson2_clk_board_info *p, *data;
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data = device_get_match_data(dev);
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if (!data)
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return -EINVAL;
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for (p = data; p->name; p++)
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clks_num++;
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clp = devm_kzalloc(dev, struct_size(clp, clk_data.hws, clks_num),
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GFP_KERNEL);
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if (!clp)
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return -ENOMEM;
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clp->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(clp->base))
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return PTR_ERR(clp->base);
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spin_lock_init(&clp->clk_lock);
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clp->clk_data.num = clks_num;
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clp->dev = dev;
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for (i = 0; i < clks_num; i++) {
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p = &data[i];
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switch (p->type) {
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case CLK_TYPE_PLL:
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hw = loongson2_clk_register(clp, p,
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&loongson2_pll_recalc_ops);
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break;
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case CLK_TYPE_SCALE:
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hw = loongson2_clk_register(clp, p,
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&loongson2_freqscale_recalc_ops);
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break;
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case CLK_TYPE_DIVIDER:
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hw = devm_clk_hw_register_divider(dev, p->name,
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p->parent_name, 0,
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clp->base + p->reg_offset,
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p->div_shift, p->div_width,
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CLK_DIVIDER_ONE_BASED,
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&clp->clk_lock);
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break;
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case CLK_TYPE_GATE:
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hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
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clp->base + p->reg_offset,
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p->bit_idx, 0,
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&clp->clk_lock);
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break;
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case CLK_TYPE_FIXED:
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hw = clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
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0, p->fixed_rate);
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break;
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default:
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return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
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}
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if (IS_ERR(hw))
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return dev_err_probe(dev, PTR_ERR(hw),
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"Register clk: %s, type: %u failed!\n",
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p->name, p->type);
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clp->clk_data.hws[p->id] = hw;
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}
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clp->clk_data);
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}
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static const struct of_device_id loongson2_clk_match_table[] = {
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{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
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{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
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{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
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{ }
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};
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MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
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static struct platform_driver loongson2_clk_driver = {
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.probe = loongson2_clk_probe,
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.driver = {
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.name = "loongson2-clk",
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.of_match_table = loongson2_clk_match_table,
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},
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};
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module_platform_driver(loongson2_clk_driver);
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|
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MODULE_DESCRIPTION("Loongson2 clock driver");
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MODULE_AUTHOR("Loongson Technology Corporation Limited");
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MODULE_LICENSE("GPL");
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