mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-12-28 16:56:26 +00:00
e70140ba0d
The continual trickle of small conversion patches is grating on me, and is really not helping. Just get rid of the 'remove_new' member function, which is just an alias for the plain 'remove', and had a comment to that effect: /* * .remove_new() is a relic from a prototype conversion of .remove(). * New drivers are supposed to implement .remove(). Once all drivers are * converted to not use .remove_new any more, it will be dropped. */ This was just a tree-wide 'sed' script that replaced '.remove_new' with '.remove', with some care taken to turn a subsequent tab into two tabs to make things line up. I did do some minimal manual whitespace adjustment for places that used spaces to line things up. Then I just removed the old (sic) .remove_new member function, and this is the end result. No more unnecessary conversion noise. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
1010 lines
21 KiB
C
1010 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PTP hardware clock driver for the FemtoClock3 family of timing and
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* synchronization devices.
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*
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* Copyright (C) 2023 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#include <linux/firmware.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/timekeeping.h>
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#include <linux/string.h>
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#include <linux/of.h>
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#include <linux/bitfield.h>
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#include <linux/mfd/rsmu.h>
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#include <linux/mfd/idtRC38xxx_reg.h>
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#include <linux/unaligned.h>
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#include "ptp_private.h"
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#include "ptp_fc3.h"
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MODULE_DESCRIPTION("Driver for IDT FemtoClock3(TM) family");
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MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
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MODULE_VERSION("1.0");
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MODULE_LICENSE("GPL");
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/*
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* The name of the firmware file to be loaded
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* over-rides any automatic selection
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*/
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static char *firmware;
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module_param(firmware, charp, 0);
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static s64 ns2counters(struct idtfc3 *idtfc3, s64 nsec, u32 *sub_ns)
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{
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s64 sync;
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s32 rem;
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if (likely(nsec >= 0)) {
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sync = div_u64_rem(nsec, idtfc3->ns_per_sync, &rem);
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*sub_ns = rem;
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} else {
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sync = -div_u64_rem(-nsec - 1, idtfc3->ns_per_sync, &rem) - 1;
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*sub_ns = idtfc3->ns_per_sync - rem - 1;
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}
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return sync * idtfc3->ns_per_sync;
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}
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static s64 tdc_meas2offset(struct idtfc3 *idtfc3, u64 meas_read)
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{
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s64 coarse, fine;
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fine = sign_extend64(FIELD_GET(FINE_MEAS_MASK, meas_read), 12);
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coarse = sign_extend64(FIELD_GET(COARSE_MEAS_MASK, meas_read), (39 - 13));
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fine = div64_s64(fine * NSEC_PER_SEC, idtfc3->tdc_apll_freq * 62LL);
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coarse = div64_s64(coarse * NSEC_PER_SEC, idtfc3->time_ref_freq);
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return coarse + fine;
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}
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static s64 tdc_offset2phase(struct idtfc3 *idtfc3, s64 offset_ns)
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{
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if (offset_ns > idtfc3->ns_per_sync / 2)
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offset_ns -= idtfc3->ns_per_sync;
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return offset_ns * idtfc3->tdc_offset_sign;
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}
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static int idtfc3_set_lpf_mode(struct idtfc3 *idtfc3, u8 mode)
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{
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int err;
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if (mode >= LPF_INVALID)
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return -EINVAL;
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if (idtfc3->lpf_mode == mode)
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return 0;
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err = regmap_bulk_write(idtfc3->regmap, LPF_MODE_CNFG, &mode, sizeof(mode));
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if (err)
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return err;
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idtfc3->lpf_mode = mode;
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return 0;
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}
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static int idtfc3_enable_lpf(struct idtfc3 *idtfc3, bool enable)
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{
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u8 val;
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int err;
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err = regmap_bulk_read(idtfc3->regmap, LPF_CTRL, &val, sizeof(val));
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if (err)
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return err;
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if (enable == true)
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val |= LPF_EN;
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else
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val &= ~LPF_EN;
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return regmap_bulk_write(idtfc3->regmap, LPF_CTRL, &val, sizeof(val));
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}
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static int idtfc3_get_time_ref_freq(struct idtfc3 *idtfc3)
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{
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int err;
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u8 buf[4];
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u8 time_ref_div;
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u8 time_clk_div;
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err = regmap_bulk_read(idtfc3->regmap, TIME_CLOCK_MEAS_DIV_CNFG, buf, sizeof(buf));
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if (err)
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return err;
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time_ref_div = FIELD_GET(TIME_REF_DIV_MASK, get_unaligned_le32(buf)) + 1;
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err = regmap_bulk_read(idtfc3->regmap, TIME_CLOCK_COUNT, buf, 1);
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if (err)
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return err;
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time_clk_div = (buf[0] & TIME_CLOCK_COUNT_MASK) + 1;
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idtfc3->time_ref_freq = idtfc3->hw_param.time_clk_freq *
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time_clk_div / time_ref_div;
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return 0;
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}
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static int idtfc3_get_tdc_offset_sign(struct idtfc3 *idtfc3)
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{
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int err;
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u8 buf[4];
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u32 val;
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u8 sig1, sig2;
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err = regmap_bulk_read(idtfc3->regmap, TIME_CLOCK_TDC_FANOUT_CNFG, buf, sizeof(buf));
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if (err)
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return err;
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val = get_unaligned_le32(buf);
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if ((val & TIME_SYNC_TO_TDC_EN) != TIME_SYNC_TO_TDC_EN) {
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dev_err(idtfc3->dev, "TIME_SYNC_TO_TDC_EN is off !!!");
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return -EINVAL;
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}
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sig1 = FIELD_GET(SIG1_MUX_SEL_MASK, val);
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sig2 = FIELD_GET(SIG2_MUX_SEL_MASK, val);
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if ((sig1 == sig2) || ((sig1 != TIME_SYNC) && (sig2 != TIME_SYNC))) {
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dev_err(idtfc3->dev, "Invalid tdc_mux_sel sig1=%d sig2=%d", sig1, sig2);
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return -EINVAL;
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} else if (sig1 == TIME_SYNC) {
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idtfc3->tdc_offset_sign = 1;
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} else if (sig2 == TIME_SYNC) {
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idtfc3->tdc_offset_sign = -1;
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}
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return 0;
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}
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static int idtfc3_lpf_bw(struct idtfc3 *idtfc3, u8 shift, u8 mult)
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{
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u8 val = FIELD_PREP(LPF_BW_SHIFT, shift) | FIELD_PREP(LPF_BW_MULT, mult);
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return regmap_bulk_write(idtfc3->regmap, LPF_BW_CNFG, &val, sizeof(val));
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}
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static int idtfc3_enable_tdc(struct idtfc3 *idtfc3, bool enable, u8 meas_mode)
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{
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int err;
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u8 val = 0;
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/* Disable TDC first */
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err = regmap_bulk_write(idtfc3->regmap, TIME_CLOCK_MEAS_CTRL, &val, sizeof(val));
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if (err)
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return err;
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if (enable == false)
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return idtfc3_lpf_bw(idtfc3, LPF_BW_SHIFT_DEFAULT, LPF_BW_MULT_DEFAULT);
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if (meas_mode >= MEAS_MODE_INVALID)
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return -EINVAL;
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/* Change TDC meas mode */
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err = regmap_bulk_write(idtfc3->regmap, TIME_CLOCK_MEAS_CNFG,
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&meas_mode, sizeof(meas_mode));
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if (err)
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return err;
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/* Enable TDC */
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val = TDC_MEAS_EN;
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if (meas_mode == CONTINUOUS)
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val |= TDC_MEAS_START;
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err = regmap_bulk_write(idtfc3->regmap, TIME_CLOCK_MEAS_CTRL, &val, sizeof(val));
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if (err)
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return err;
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return idtfc3_lpf_bw(idtfc3, LPF_BW_SHIFT_1PPS, LPF_BW_MULT_DEFAULT);
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}
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static bool get_tdc_meas(struct idtfc3 *idtfc3, s64 *offset_ns)
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{
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bool valid = false;
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u8 buf[9];
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u8 val;
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int err;
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while (true) {
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err = regmap_bulk_read(idtfc3->regmap, TDC_FIFO_STS,
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&val, sizeof(val));
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if (err)
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return false;
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if (val & FIFO_EMPTY)
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break;
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err = regmap_bulk_read(idtfc3->regmap, TDC_FIFO_READ_REQ,
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&buf, sizeof(buf));
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if (err)
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return false;
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valid = true;
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}
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if (valid)
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*offset_ns = tdc_meas2offset(idtfc3, get_unaligned_le64(&buf[1]));
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return valid;
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}
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static int check_tdc_fifo_overrun(struct idtfc3 *idtfc3)
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{
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u8 val;
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int err;
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/* Check if FIFO is overrun */
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err = regmap_bulk_read(idtfc3->regmap, TDC_FIFO_STS, &val, sizeof(val));
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if (err)
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return err;
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if (!(val & FIFO_FULL))
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return 0;
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dev_warn(idtfc3->dev, "TDC FIFO overrun !!!");
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err = idtfc3_enable_tdc(idtfc3, true, CONTINUOUS);
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if (err)
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return err;
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return 0;
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}
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static int get_tdc_meas_continuous(struct idtfc3 *idtfc3)
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{
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int err;
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s64 offset_ns;
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struct ptp_clock_event event;
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err = check_tdc_fifo_overrun(idtfc3);
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if (err)
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return err;
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if (get_tdc_meas(idtfc3, &offset_ns) && offset_ns >= 0) {
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event.index = 0;
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event.offset = tdc_offset2phase(idtfc3, offset_ns);
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event.type = PTP_CLOCK_EXTOFF;
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ptp_clock_event(idtfc3->ptp_clock, &event);
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}
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return 0;
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}
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static int idtfc3_read_subcounter(struct idtfc3 *idtfc3)
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{
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u8 buf[5] = {0};
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int err;
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err = regmap_bulk_read(idtfc3->regmap, TOD_COUNTER_READ_REQ,
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&buf, sizeof(buf));
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if (err)
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return err;
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/* sync_counter_value is [31:82] and sub_sync_counter_value is [0:30] */
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return get_unaligned_le32(&buf[1]) & SUB_SYNC_COUNTER_MASK;
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}
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static int idtfc3_tod_update_is_done(struct idtfc3 *idtfc3)
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{
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int err;
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u8 req;
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err = read_poll_timeout_atomic(regmap_bulk_read, err, !req, USEC_PER_MSEC,
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idtfc3->tc_write_timeout, true, idtfc3->regmap,
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TOD_SYNC_LOAD_REQ_CTRL, &req, 1);
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if (err)
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dev_err(idtfc3->dev, "TOD counter write timeout !!!");
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return err;
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}
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static int idtfc3_write_subcounter(struct idtfc3 *idtfc3, u32 counter)
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{
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u8 buf[18] = {0};
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int err;
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/* sync_counter_value is [31:82] and sub_sync_counter_value is [0:30] */
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put_unaligned_le32(counter & SUB_SYNC_COUNTER_MASK, &buf[0]);
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buf[16] = SUB_SYNC_LOAD_ENABLE | SYNC_LOAD_ENABLE;
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buf[17] = SYNC_LOAD_REQ;
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err = regmap_bulk_write(idtfc3->regmap, TOD_SYNC_LOAD_VAL_CTRL,
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&buf, sizeof(buf));
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if (err)
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return err;
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return idtfc3_tod_update_is_done(idtfc3);
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}
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static int idtfc3_timecounter_update(struct idtfc3 *idtfc3, u32 counter, s64 ns)
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{
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int err;
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err = idtfc3_write_subcounter(idtfc3, counter);
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if (err)
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return err;
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/* Update time counter */
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idtfc3->ns = ns;
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idtfc3->last_counter = counter;
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return 0;
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}
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static int idtfc3_timecounter_read(struct idtfc3 *idtfc3)
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{
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int now, delta;
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now = idtfc3_read_subcounter(idtfc3);
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if (now < 0)
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return now;
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/* calculate the delta since the last idtfc3_timecounter_read(): */
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if (now >= idtfc3->last_counter)
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delta = now - idtfc3->last_counter;
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else
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delta = idtfc3->sub_sync_count - idtfc3->last_counter + now;
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/* Update time counter */
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idtfc3->ns += delta * idtfc3->ns_per_counter;
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idtfc3->last_counter = now;
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return 0;
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}
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static int _idtfc3_gettime(struct idtfc3 *idtfc3, struct timespec64 *ts)
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{
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int err;
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err = idtfc3_timecounter_read(idtfc3);
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if (err)
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return err;
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*ts = ns_to_timespec64(idtfc3->ns);
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return 0;
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}
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static int idtfc3_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
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int err;
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mutex_lock(idtfc3->lock);
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err = _idtfc3_gettime(idtfc3, ts);
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mutex_unlock(idtfc3->lock);
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return err;
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}
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static int _idtfc3_settime(struct idtfc3 *idtfc3, const struct timespec64 *ts)
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{
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s64 offset_ns, now_ns;
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u32 counter, sub_ns;
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int now;
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if (timespec64_valid(ts) == false) {
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dev_err(idtfc3->dev, "%s: invalid timespec", __func__);
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return -EINVAL;
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}
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now = idtfc3_read_subcounter(idtfc3);
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if (now < 0)
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return now;
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offset_ns = (idtfc3->sub_sync_count - now) * idtfc3->ns_per_counter;
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now_ns = timespec64_to_ns(ts);
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(void)ns2counters(idtfc3, offset_ns + now_ns, &sub_ns);
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counter = sub_ns / idtfc3->ns_per_counter;
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return idtfc3_timecounter_update(idtfc3, counter, now_ns);
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}
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static int idtfc3_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
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{
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struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
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int err;
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mutex_lock(idtfc3->lock);
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err = _idtfc3_settime(idtfc3, ts);
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mutex_unlock(idtfc3->lock);
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return err;
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}
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static int _idtfc3_adjtime(struct idtfc3 *idtfc3, s64 delta)
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{
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/*
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* The TOD counter can be synchronously loaded with any value,
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* to be loaded on the next Time Sync pulse
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*/
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s64 sync_ns;
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u32 sub_ns;
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u32 counter;
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if (idtfc3->ns + delta < 0) {
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dev_err(idtfc3->dev, "%lld ns adj is too large", delta);
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return -EINVAL;
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}
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sync_ns = ns2counters(idtfc3, delta + idtfc3->ns_per_sync, &sub_ns);
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counter = sub_ns / idtfc3->ns_per_counter;
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return idtfc3_timecounter_update(idtfc3, counter, idtfc3->ns + sync_ns +
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counter * idtfc3->ns_per_counter);
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}
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static int idtfc3_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
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int err;
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mutex_lock(idtfc3->lock);
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err = _idtfc3_adjtime(idtfc3, delta);
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mutex_unlock(idtfc3->lock);
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return err;
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}
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static int _idtfc3_adjphase(struct idtfc3 *idtfc3, s32 delta)
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{
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u8 buf[8] = {0};
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int err;
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s64 pcw;
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err = idtfc3_set_lpf_mode(idtfc3, LPF_WP);
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if (err)
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return err;
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/*
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* Phase Control Word unit is: 10^9 / (TDC_APLL_FREQ * 124)
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*
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* delta * TDC_APLL_FREQ * 124
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* PCW = ---------------------------
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* 10^9
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*
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*/
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pcw = div_s64((s64)delta * idtfc3->tdc_apll_freq * 124, NSEC_PER_SEC);
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put_unaligned_le64(pcw, buf);
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return regmap_bulk_write(idtfc3->regmap, LPF_WR_PHASE_CTRL, buf, sizeof(buf));
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}
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static int idtfc3_adjphase(struct ptp_clock_info *ptp, s32 delta)
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{
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struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
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int err;
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mutex_lock(idtfc3->lock);
|
|
err = _idtfc3_adjphase(idtfc3, delta);
|
|
mutex_unlock(idtfc3->lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int _idtfc3_adjfine(struct idtfc3 *idtfc3, long scaled_ppm)
|
|
{
|
|
u8 buf[8] = {0};
|
|
int err;
|
|
s64 fcw;
|
|
|
|
err = idtfc3_set_lpf_mode(idtfc3, LPF_WF);
|
|
if (err)
|
|
return err;
|
|
|
|
/*
|
|
* Frequency Control Word unit is: 2^-44 * 10^6 ppm
|
|
*
|
|
* adjfreq:
|
|
* ppb * 2^44
|
|
* FCW = ----------
|
|
* 10^9
|
|
*
|
|
* adjfine:
|
|
* ppm_16 * 2^28
|
|
* FCW = -------------
|
|
* 10^6
|
|
*/
|
|
fcw = scaled_ppm * BIT(28);
|
|
fcw = div_s64(fcw, 1000000);
|
|
|
|
put_unaligned_le64(fcw, buf);
|
|
|
|
return regmap_bulk_write(idtfc3->regmap, LPF_WR_FREQ_CTRL, buf, sizeof(buf));
|
|
}
|
|
|
|
static int idtfc3_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
|
|
{
|
|
struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
|
|
int err;
|
|
|
|
mutex_lock(idtfc3->lock);
|
|
err = _idtfc3_adjfine(idtfc3, scaled_ppm);
|
|
mutex_unlock(idtfc3->lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idtfc3_enable(struct ptp_clock_info *ptp,
|
|
struct ptp_clock_request *rq, int on)
|
|
{
|
|
struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
|
|
int err = -EOPNOTSUPP;
|
|
|
|
mutex_lock(idtfc3->lock);
|
|
switch (rq->type) {
|
|
case PTP_CLK_REQ_PEROUT:
|
|
if (!on)
|
|
err = 0;
|
|
/* Only accept a 1-PPS aligned to the second. */
|
|
else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
|
|
rq->perout.period.nsec)
|
|
err = -ERANGE;
|
|
else
|
|
err = 0;
|
|
break;
|
|
case PTP_CLK_REQ_EXTTS:
|
|
if (on) {
|
|
/* Only accept requests for external phase offset */
|
|
if ((rq->extts.flags & PTP_EXT_OFFSET) != (PTP_EXT_OFFSET))
|
|
err = -EOPNOTSUPP;
|
|
else
|
|
err = idtfc3_enable_tdc(idtfc3, true, CONTINUOUS);
|
|
} else {
|
|
err = idtfc3_enable_tdc(idtfc3, false, MEAS_MODE_INVALID);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
mutex_unlock(idtfc3->lock);
|
|
|
|
if (err)
|
|
dev_err(idtfc3->dev, "Failed in %s with err %d!", __func__, err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static long idtfc3_aux_work(struct ptp_clock_info *ptp)
|
|
{
|
|
struct idtfc3 *idtfc3 = container_of(ptp, struct idtfc3, caps);
|
|
static int tdc_get;
|
|
|
|
mutex_lock(idtfc3->lock);
|
|
tdc_get %= TDC_GET_PERIOD;
|
|
if ((tdc_get == 0) || (tdc_get == TDC_GET_PERIOD / 2))
|
|
idtfc3_timecounter_read(idtfc3);
|
|
get_tdc_meas_continuous(idtfc3);
|
|
tdc_get++;
|
|
mutex_unlock(idtfc3->lock);
|
|
|
|
return idtfc3->tc_update_period;
|
|
}
|
|
|
|
static const struct ptp_clock_info idtfc3_caps = {
|
|
.owner = THIS_MODULE,
|
|
.max_adj = MAX_FFO_PPB,
|
|
.n_per_out = 1,
|
|
.n_ext_ts = 1,
|
|
.adjphase = &idtfc3_adjphase,
|
|
.adjfine = &idtfc3_adjfine,
|
|
.adjtime = &idtfc3_adjtime,
|
|
.gettime64 = &idtfc3_gettime,
|
|
.settime64 = &idtfc3_settime,
|
|
.enable = &idtfc3_enable,
|
|
.do_aux_work = &idtfc3_aux_work,
|
|
};
|
|
|
|
static int idtfc3_hw_calibrate(struct idtfc3 *idtfc3)
|
|
{
|
|
int err = 0;
|
|
u8 val;
|
|
|
|
mdelay(10);
|
|
/*
|
|
* Toggle TDC_DAC_RECAL_REQ:
|
|
* (1) set tdc_en to 1
|
|
* (2) set tdc_dac_recal_req to 0
|
|
* (3) set tdc_dac_recal_req to 1
|
|
*/
|
|
val = TDC_EN;
|
|
err = regmap_bulk_write(idtfc3->regmap, TDC_CTRL,
|
|
&val, sizeof(val));
|
|
if (err)
|
|
return err;
|
|
val = TDC_EN | TDC_DAC_RECAL_REQ;
|
|
err = regmap_bulk_write(idtfc3->regmap, TDC_CTRL,
|
|
&val, sizeof(val));
|
|
if (err)
|
|
return err;
|
|
mdelay(10);
|
|
|
|
/*
|
|
* Toggle APLL_REINIT:
|
|
* (1) set apll_reinit to 0
|
|
* (2) set apll_reinit to 1
|
|
*/
|
|
val = 0;
|
|
err = regmap_bulk_write(idtfc3->regmap, SOFT_RESET_CTRL,
|
|
&val, sizeof(val));
|
|
if (err)
|
|
return err;
|
|
val = APLL_REINIT;
|
|
err = regmap_bulk_write(idtfc3->regmap, SOFT_RESET_CTRL,
|
|
&val, sizeof(val));
|
|
if (err)
|
|
return err;
|
|
mdelay(10);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idtfc3_init_timecounter(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
u32 period_ms;
|
|
|
|
period_ms = idtfc3->sub_sync_count * MSEC_PER_SEC /
|
|
idtfc3->hw_param.time_clk_freq;
|
|
|
|
idtfc3->tc_update_period = msecs_to_jiffies(period_ms / TDC_GET_PERIOD);
|
|
idtfc3->tc_write_timeout = period_ms * USEC_PER_MSEC;
|
|
|
|
err = idtfc3_timecounter_update(idtfc3, 0, 0);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_timecounter_read(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
ptp_schedule_worker(idtfc3->ptp_clock, idtfc3->tc_update_period);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_get_tdc_apll_freq(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
u8 tdc_fb_div_int;
|
|
u8 tdc_ref_div;
|
|
struct idtfc3_hw_param *param = &idtfc3->hw_param;
|
|
|
|
err = regmap_bulk_read(idtfc3->regmap, TDC_REF_DIV_CNFG,
|
|
&tdc_ref_div, sizeof(tdc_ref_div));
|
|
if (err)
|
|
return err;
|
|
|
|
err = regmap_bulk_read(idtfc3->regmap, TDC_FB_DIV_INT_CNFG,
|
|
&tdc_fb_div_int, sizeof(tdc_fb_div_int));
|
|
if (err)
|
|
return err;
|
|
|
|
tdc_fb_div_int &= TDC_FB_DIV_INT_MASK;
|
|
tdc_ref_div &= TDC_REF_DIV_CONFIG_MASK;
|
|
|
|
idtfc3->tdc_apll_freq = div_u64(param->xtal_freq * (u64)tdc_fb_div_int,
|
|
1 << tdc_ref_div);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_get_fod(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
u8 fod;
|
|
|
|
err = regmap_bulk_read(idtfc3->regmap, TIME_CLOCK_SRC, &fod, sizeof(fod));
|
|
if (err)
|
|
return err;
|
|
|
|
switch (fod) {
|
|
case 0:
|
|
idtfc3->fod_n = FOD_0;
|
|
break;
|
|
case 1:
|
|
idtfc3->fod_n = FOD_1;
|
|
break;
|
|
case 2:
|
|
idtfc3->fod_n = FOD_2;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_get_sync_count(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
u8 buf[4];
|
|
|
|
err = regmap_bulk_read(idtfc3->regmap, SUB_SYNC_GEN_CNFG, buf, sizeof(buf));
|
|
if (err)
|
|
return err;
|
|
|
|
idtfc3->sub_sync_count = (get_unaligned_le32(buf) & SUB_SYNC_COUNTER_MASK) + 1;
|
|
idtfc3->ns_per_counter = NSEC_PER_SEC / idtfc3->hw_param.time_clk_freq;
|
|
idtfc3->ns_per_sync = idtfc3->sub_sync_count * idtfc3->ns_per_counter;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_setup_hw_param(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
|
|
err = idtfc3_get_fod(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_get_sync_count(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_get_time_ref_freq(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
return idtfc3_get_tdc_apll_freq(idtfc3);
|
|
}
|
|
|
|
static int idtfc3_configure_hw(struct idtfc3 *idtfc3)
|
|
{
|
|
int err = 0;
|
|
|
|
err = idtfc3_hw_calibrate(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_enable_lpf(idtfc3, true);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_enable_tdc(idtfc3, false, MEAS_MODE_INVALID);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_get_tdc_offset_sign(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
return idtfc3_setup_hw_param(idtfc3);
|
|
}
|
|
|
|
static int idtfc3_set_overhead(struct idtfc3 *idtfc3)
|
|
{
|
|
s64 current_ns = 0;
|
|
s64 lowest_ns = 0;
|
|
int err;
|
|
u8 i;
|
|
ktime_t start;
|
|
ktime_t stop;
|
|
ktime_t diff;
|
|
|
|
char buf[18] = {0};
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
start = ktime_get_raw();
|
|
|
|
err = regmap_bulk_write(idtfc3->regmap, TOD_SYNC_LOAD_VAL_CTRL,
|
|
&buf, sizeof(buf));
|
|
if (err)
|
|
return err;
|
|
|
|
stop = ktime_get_raw();
|
|
|
|
diff = ktime_sub(stop, start);
|
|
|
|
current_ns = ktime_to_ns(diff);
|
|
|
|
if (i == 0) {
|
|
lowest_ns = current_ns;
|
|
} else {
|
|
if (current_ns < lowest_ns)
|
|
lowest_ns = current_ns;
|
|
}
|
|
}
|
|
|
|
idtfc3->tod_write_overhead = lowest_ns;
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idtfc3_enable_ptp(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
|
|
idtfc3->caps = idtfc3_caps;
|
|
snprintf(idtfc3->caps.name, sizeof(idtfc3->caps.name), "IDT FC3W");
|
|
idtfc3->ptp_clock = ptp_clock_register(&idtfc3->caps, NULL);
|
|
|
|
if (IS_ERR(idtfc3->ptp_clock)) {
|
|
err = PTR_ERR(idtfc3->ptp_clock);
|
|
idtfc3->ptp_clock = NULL;
|
|
return err;
|
|
}
|
|
|
|
err = idtfc3_set_overhead(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idtfc3_init_timecounter(idtfc3);
|
|
if (err)
|
|
return err;
|
|
|
|
dev_info(idtfc3->dev, "TIME_SYNC_CHANNEL registered as ptp%d",
|
|
idtfc3->ptp_clock->index);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_load_firmware(struct idtfc3 *idtfc3)
|
|
{
|
|
char fname[128] = FW_FILENAME;
|
|
const struct firmware *fw;
|
|
struct idtfc3_fwrc *rec;
|
|
u16 addr;
|
|
u8 val;
|
|
int err;
|
|
s32 len;
|
|
|
|
idtfc3_default_hw_param(&idtfc3->hw_param);
|
|
|
|
if (firmware) /* module parameter */
|
|
snprintf(fname, sizeof(fname), "%s", firmware);
|
|
|
|
dev_info(idtfc3->dev, "requesting firmware '%s'\n", fname);
|
|
|
|
err = request_firmware(&fw, fname, idtfc3->dev);
|
|
|
|
if (err) {
|
|
dev_err(idtfc3->dev,
|
|
"requesting firmware failed with err %d!\n", err);
|
|
return err;
|
|
}
|
|
|
|
dev_dbg(idtfc3->dev, "firmware size %zu bytes\n", fw->size);
|
|
|
|
rec = (struct idtfc3_fwrc *)fw->data;
|
|
|
|
for (len = fw->size; len > 0; len -= sizeof(*rec)) {
|
|
if (rec->reserved) {
|
|
dev_err(idtfc3->dev,
|
|
"bad firmware, reserved field non-zero\n");
|
|
err = -EINVAL;
|
|
} else {
|
|
val = rec->value;
|
|
addr = rec->hiaddr << 8 | rec->loaddr;
|
|
|
|
rec++;
|
|
|
|
err = idtfc3_set_hw_param(&idtfc3->hw_param, addr, val);
|
|
}
|
|
|
|
if (err != -EINVAL) {
|
|
err = 0;
|
|
|
|
/* Max register */
|
|
if (addr >= 0xE88)
|
|
continue;
|
|
|
|
err = regmap_bulk_write(idtfc3->regmap, addr,
|
|
&val, sizeof(val));
|
|
}
|
|
|
|
if (err)
|
|
goto out;
|
|
}
|
|
|
|
err = idtfc3_configure_hw(idtfc3);
|
|
out:
|
|
release_firmware(fw);
|
|
return err;
|
|
}
|
|
|
|
static int idtfc3_read_device_id(struct idtfc3 *idtfc3, u16 *device_id)
|
|
{
|
|
int err;
|
|
u8 buf[2] = {0};
|
|
|
|
err = regmap_bulk_read(idtfc3->regmap, DEVICE_ID,
|
|
&buf, sizeof(buf));
|
|
if (err) {
|
|
dev_err(idtfc3->dev, "%s failed with %d", __func__, err);
|
|
return err;
|
|
}
|
|
|
|
*device_id = get_unaligned_le16(buf);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_check_device_compatibility(struct idtfc3 *idtfc3)
|
|
{
|
|
int err;
|
|
u16 device_id;
|
|
|
|
err = idtfc3_read_device_id(idtfc3, &device_id);
|
|
if (err)
|
|
return err;
|
|
|
|
if ((device_id & DEVICE_ID_MASK) == 0) {
|
|
dev_err(idtfc3->dev, "invalid device");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idtfc3_probe(struct platform_device *pdev)
|
|
{
|
|
struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
|
|
struct idtfc3 *idtfc3;
|
|
int err;
|
|
|
|
idtfc3 = devm_kzalloc(&pdev->dev, sizeof(struct idtfc3), GFP_KERNEL);
|
|
|
|
if (!idtfc3)
|
|
return -ENOMEM;
|
|
|
|
idtfc3->dev = &pdev->dev;
|
|
idtfc3->mfd = pdev->dev.parent;
|
|
idtfc3->lock = &ddata->lock;
|
|
idtfc3->regmap = ddata->regmap;
|
|
|
|
mutex_lock(idtfc3->lock);
|
|
|
|
err = idtfc3_check_device_compatibility(idtfc3);
|
|
if (err) {
|
|
mutex_unlock(idtfc3->lock);
|
|
return err;
|
|
}
|
|
|
|
err = idtfc3_load_firmware(idtfc3);
|
|
if (err) {
|
|
if (err == -ENOENT) {
|
|
mutex_unlock(idtfc3->lock);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
dev_warn(idtfc3->dev, "loading firmware failed with %d", err);
|
|
}
|
|
|
|
err = idtfc3_enable_ptp(idtfc3);
|
|
if (err) {
|
|
dev_err(idtfc3->dev, "idtfc3_enable_ptp failed with %d", err);
|
|
mutex_unlock(idtfc3->lock);
|
|
return err;
|
|
}
|
|
|
|
mutex_unlock(idtfc3->lock);
|
|
|
|
platform_set_drvdata(pdev, idtfc3);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void idtfc3_remove(struct platform_device *pdev)
|
|
{
|
|
struct idtfc3 *idtfc3 = platform_get_drvdata(pdev);
|
|
|
|
ptp_clock_unregister(idtfc3->ptp_clock);
|
|
}
|
|
|
|
static struct platform_driver idtfc3_driver = {
|
|
.driver = {
|
|
.name = "rc38xxx-phc",
|
|
},
|
|
.probe = idtfc3_probe,
|
|
.remove = idtfc3_remove,
|
|
};
|
|
|
|
module_platform_driver(idtfc3_driver);
|