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3cf67f3769
Add support for Airoha EN7851 watchdog. This is a very basic watchdog with no pretimeout support, max timeout is 28 seconds and it ticks based on half the SoC BUS clock. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20241011104411.28659-2-ansuelsmth@gmail.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
217 lines
5.6 KiB
C
217 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Airoha Watchdog Driver
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*
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* Copyright (c) 2024, AIROHA All rights reserved.
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*
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* Mayur Kumar <mayur.kumar@airoha.com>
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* Christian Marangi <ansuelsmth@gmail.com>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/math.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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/* Base address of timer and watchdog registers */
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#define TIMER_CTRL 0x0
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#define WDT_ENABLE BIT(25)
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#define WDT_TIMER_INTERRUPT BIT(21)
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/* Timer3 is used as Watchdog Timer */
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#define WDT_TIMER_ENABLE BIT(5)
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#define WDT_TIMER_LOAD_VALUE 0x2c
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#define WDT_TIMER_CUR_VALUE 0x30
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#define WDT_TIMER_VAL GENMASK(31, 0)
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#define WDT_RELOAD 0x38
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#define WDT_RLD BIT(0)
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/* Airoha watchdog structure description */
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struct airoha_wdt_desc {
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struct watchdog_device wdog_dev;
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unsigned int wdt_freq;
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void __iomem *base;
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};
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#define WDT_HEARTBEAT 24
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static int heartbeat = WDT_HEARTBEAT;
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. (default="
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__MODULE_STRING(WDT_HEARTBEAT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static int airoha_wdt_start(struct watchdog_device *wdog_dev)
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{
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struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdog_dev);
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u32 val;
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val = readl(airoha_wdt->base + TIMER_CTRL);
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val |= (WDT_TIMER_ENABLE | WDT_ENABLE | WDT_TIMER_INTERRUPT);
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writel(val, airoha_wdt->base + TIMER_CTRL);
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val = wdog_dev->timeout * airoha_wdt->wdt_freq;
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writel(val, airoha_wdt->base + WDT_TIMER_LOAD_VALUE);
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return 0;
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}
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static int airoha_wdt_stop(struct watchdog_device *wdog_dev)
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{
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struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdog_dev);
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u32 val;
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val = readl(airoha_wdt->base + TIMER_CTRL);
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val &= (~WDT_ENABLE & ~WDT_TIMER_ENABLE);
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writel(val, airoha_wdt->base + TIMER_CTRL);
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return 0;
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}
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static int airoha_wdt_ping(struct watchdog_device *wdog_dev)
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{
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struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdog_dev);
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u32 val;
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val = readl(airoha_wdt->base + WDT_RELOAD);
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val |= WDT_RLD;
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writel(val, airoha_wdt->base + WDT_RELOAD);
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return 0;
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}
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static int airoha_wdt_set_timeout(struct watchdog_device *wdog_dev, unsigned int timeout)
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{
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wdog_dev->timeout = timeout;
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if (watchdog_active(wdog_dev)) {
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airoha_wdt_stop(wdog_dev);
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return airoha_wdt_start(wdog_dev);
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}
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return 0;
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}
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static unsigned int airoha_wdt_get_timeleft(struct watchdog_device *wdog_dev)
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{
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struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdog_dev);
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u32 val;
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val = readl(airoha_wdt->base + WDT_TIMER_CUR_VALUE);
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return DIV_ROUND_UP(val, airoha_wdt->wdt_freq);
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}
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static const struct watchdog_info airoha_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
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.identity = "Airoha Watchdog",
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};
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static const struct watchdog_ops airoha_wdt_ops = {
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.owner = THIS_MODULE,
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.start = airoha_wdt_start,
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.stop = airoha_wdt_stop,
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.ping = airoha_wdt_ping,
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.set_timeout = airoha_wdt_set_timeout,
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.get_timeleft = airoha_wdt_get_timeleft,
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};
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static int airoha_wdt_probe(struct platform_device *pdev)
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{
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struct airoha_wdt_desc *airoha_wdt;
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struct watchdog_device *wdog_dev;
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struct device *dev = &pdev->dev;
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struct clk *bus_clk;
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int ret;
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airoha_wdt = devm_kzalloc(dev, sizeof(*airoha_wdt), GFP_KERNEL);
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if (!airoha_wdt)
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return -ENOMEM;
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airoha_wdt->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(airoha_wdt->base))
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return PTR_ERR(airoha_wdt->base);
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bus_clk = devm_clk_get_enabled(dev, "bus");
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if (IS_ERR(bus_clk))
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return dev_err_probe(dev, PTR_ERR(bus_clk),
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"failed to enable bus clock\n");
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/* Watchdog ticks at half the bus rate */
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airoha_wdt->wdt_freq = clk_get_rate(bus_clk) / 2;
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/* Initialize struct watchdog device */
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wdog_dev = &airoha_wdt->wdog_dev;
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wdog_dev->timeout = heartbeat;
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wdog_dev->info = &airoha_wdt_info;
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wdog_dev->ops = &airoha_wdt_ops;
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/* Bus 300MHz, watchdog 150MHz, 28 seconds */
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wdog_dev->max_timeout = FIELD_MAX(WDT_TIMER_VAL) / airoha_wdt->wdt_freq;
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wdog_dev->parent = dev;
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watchdog_set_drvdata(wdog_dev, airoha_wdt);
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watchdog_set_nowayout(wdog_dev, nowayout);
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watchdog_stop_on_unregister(wdog_dev);
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ret = devm_watchdog_register_device(dev, wdog_dev);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, airoha_wdt);
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return 0;
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}
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static int airoha_wdt_suspend(struct device *dev)
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{
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struct airoha_wdt_desc *airoha_wdt = dev_get_drvdata(dev);
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if (watchdog_active(&airoha_wdt->wdog_dev))
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airoha_wdt_stop(&airoha_wdt->wdog_dev);
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return 0;
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}
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static int airoha_wdt_resume(struct device *dev)
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{
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struct airoha_wdt_desc *airoha_wdt = dev_get_drvdata(dev);
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if (watchdog_active(&airoha_wdt->wdog_dev)) {
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airoha_wdt_start(&airoha_wdt->wdog_dev);
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airoha_wdt_ping(&airoha_wdt->wdog_dev);
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}
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return 0;
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}
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static const struct of_device_id airoha_wdt_of_match[] = {
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{ .compatible = "airoha,en7581-wdt", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, airoha_wdt_of_match);
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static DEFINE_SIMPLE_DEV_PM_OPS(airoha_wdt_pm_ops, airoha_wdt_suspend, airoha_wdt_resume);
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static struct platform_driver airoha_wdt_driver = {
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.probe = airoha_wdt_probe,
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.driver = {
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.name = "airoha-wdt",
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.pm = pm_sleep_ptr(&airoha_wdt_pm_ops),
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.of_match_table = airoha_wdt_of_match,
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},
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};
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module_platform_driver(airoha_wdt_driver);
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MODULE_AUTHOR("Mayur Kumar <mayur.kumar@airoha.com>");
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MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
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MODULE_DESCRIPTION("Airoha EN7581 Watchdog Driver");
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MODULE_LICENSE("GPL");
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