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3ab1663af6
The STM32MP15xx IWDG adds registers which permit this IP to generate pretimeout interrupt. This interrupt can also be used to wake the CPU from suspend. Implement support for generating this interrupt and let userspace configure the pretimeout. In case the pretimeout is not configured by user, set pretimeout to 3/4 of the WDT timeout cycle. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Clément Le Goffic <clement.legoffic@foss.st.com> Tested-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20240415134903.8084-1-marex@denx.de Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
394 lines
9.9 KiB
C
394 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for STM32 Independent Watchdog
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*
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* Copyright (C) STMicroelectronics 2017
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* Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
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*
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* This driver is based on tegra_wdt.c
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/watchdog.h>
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#define DEFAULT_TIMEOUT 10
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/* IWDG registers */
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#define IWDG_KR 0x00 /* Key register */
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#define IWDG_PR 0x04 /* Prescaler Register */
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#define IWDG_RLR 0x08 /* ReLoad Register */
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#define IWDG_SR 0x0C /* Status Register */
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#define IWDG_WINR 0x10 /* Windows Register */
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#define IWDG_EWCR 0x14 /* Early Wake-up Register */
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/* IWDG_KR register bit mask */
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#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
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#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
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#define KR_KEY_EWA 0x5555 /* write access enable */
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#define KR_KEY_DWA 0x0000 /* write access disable */
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/* IWDG_PR register */
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#define PR_SHIFT 2
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#define PR_MIN BIT(PR_SHIFT)
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/* IWDG_RLR register values */
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#define RLR_MIN 0x2 /* min value recommended */
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#define RLR_MAX GENMASK(11, 0) /* max value of reload register */
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/* IWDG_SR register bit mask */
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#define SR_PVU BIT(0) /* Watchdog prescaler value update */
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#define SR_RVU BIT(1) /* Watchdog counter reload value update */
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#define EWCR_EWIT GENMASK(11, 0) /* Watchdog counter window value */
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#define EWCR_EWIC BIT(14) /* Watchdog early interrupt acknowledge */
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#define EWCR_EWIE BIT(15) /* Watchdog early interrupt enable */
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/* set timeout to 100000 us */
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#define TIMEOUT_US 100000
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#define SLEEP_US 1000
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struct stm32_iwdg_data {
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bool has_pclk;
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bool has_early_wakeup;
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u32 max_prescaler;
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};
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static const struct stm32_iwdg_data stm32_iwdg_data = {
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.has_pclk = false,
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.has_early_wakeup = false,
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.max_prescaler = 256,
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};
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static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
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.has_pclk = true,
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.has_early_wakeup = true,
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.max_prescaler = 1024,
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};
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struct stm32_iwdg {
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struct watchdog_device wdd;
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const struct stm32_iwdg_data *data;
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void __iomem *regs;
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struct clk *clk_lsi;
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struct clk *clk_pclk;
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unsigned int rate;
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};
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static inline u32 reg_read(void __iomem *base, u32 reg)
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{
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return readl_relaxed(base + reg);
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}
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static inline void reg_write(void __iomem *base, u32 reg, u32 val)
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{
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writel_relaxed(val, base + reg);
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}
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static int stm32_iwdg_start(struct watchdog_device *wdd)
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{
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struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
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u32 tout, ptot, presc, iwdg_rlr, iwdg_ewcr, iwdg_pr, iwdg_sr;
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int ret;
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dev_dbg(wdd->parent, "%s\n", __func__);
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if (!wdd->pretimeout)
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wdd->pretimeout = 3 * wdd->timeout / 4;
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tout = clamp_t(unsigned int, wdd->timeout,
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wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
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ptot = clamp_t(unsigned int, tout - wdd->pretimeout,
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wdd->min_timeout, tout);
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presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
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/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
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presc = roundup_pow_of_two(presc);
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iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
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iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
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iwdg_ewcr = ((ptot * wdt->rate) / presc) - 1;
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/* enable write access */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
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/* set prescaler & reload registers */
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reg_write(wdt->regs, IWDG_PR, iwdg_pr);
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reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
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if (wdt->data->has_early_wakeup)
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reg_write(wdt->regs, IWDG_EWCR, iwdg_ewcr | EWCR_EWIE);
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reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
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/* wait for the registers to be updated (max 100ms) */
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ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
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!(iwdg_sr & (SR_PVU | SR_RVU)),
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SLEEP_US, TIMEOUT_US);
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if (ret) {
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dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
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return ret;
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}
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/* reload watchdog */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
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return 0;
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}
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static int stm32_iwdg_ping(struct watchdog_device *wdd)
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{
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struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
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dev_dbg(wdd->parent, "%s\n", __func__);
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/* reload watchdog */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
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return 0;
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}
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static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
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wdd->timeout = timeout;
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if (watchdog_active(wdd))
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return stm32_iwdg_start(wdd);
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return 0;
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}
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static int stm32_iwdg_set_pretimeout(struct watchdog_device *wdd,
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unsigned int pretimeout)
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{
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dev_dbg(wdd->parent, "%s pretimeout: %d sec\n", __func__, pretimeout);
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wdd->pretimeout = pretimeout;
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if (watchdog_active(wdd))
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return stm32_iwdg_start(wdd);
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return 0;
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}
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static irqreturn_t stm32_iwdg_isr(int irq, void *wdog_arg)
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{
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struct watchdog_device *wdd = wdog_arg;
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struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
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u32 reg;
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reg = reg_read(wdt->regs, IWDG_EWCR);
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reg |= EWCR_EWIC;
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reg_write(wdt->regs, IWDG_EWCR, reg);
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watchdog_notify_pretimeout(wdd);
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return IRQ_HANDLED;
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}
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static void stm32_clk_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int stm32_iwdg_clk_init(struct platform_device *pdev,
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struct stm32_iwdg *wdt)
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{
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struct device *dev = &pdev->dev;
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u32 ret;
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wdt->clk_lsi = devm_clk_get(dev, "lsi");
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if (IS_ERR(wdt->clk_lsi))
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return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
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/* optional peripheral clock */
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if (wdt->data->has_pclk) {
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wdt->clk_pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(wdt->clk_pclk))
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return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
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"Unable to get pclk clock\n");
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ret = clk_prepare_enable(wdt->clk_pclk);
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if (ret) {
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dev_err(dev, "Unable to prepare pclk clock\n");
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return ret;
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}
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ret = devm_add_action_or_reset(dev,
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stm32_clk_disable_unprepare,
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wdt->clk_pclk);
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if (ret)
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return ret;
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}
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ret = clk_prepare_enable(wdt->clk_lsi);
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if (ret) {
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dev_err(dev, "Unable to prepare lsi clock\n");
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return ret;
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}
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ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
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wdt->clk_lsi);
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if (ret)
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return ret;
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wdt->rate = clk_get_rate(wdt->clk_lsi);
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return 0;
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}
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static const struct watchdog_info stm32_iwdg_info = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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.identity = "STM32 Independent Watchdog",
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};
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static const struct watchdog_info stm32_iwdg_preinfo = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING |
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WDIOF_PRETIMEOUT,
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.identity = "STM32 Independent Watchdog",
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};
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static const struct watchdog_ops stm32_iwdg_ops = {
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.owner = THIS_MODULE,
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.start = stm32_iwdg_start,
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.ping = stm32_iwdg_ping,
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.set_timeout = stm32_iwdg_set_timeout,
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.set_pretimeout = stm32_iwdg_set_pretimeout,
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};
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static const struct of_device_id stm32_iwdg_of_match[] = {
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{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
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{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
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{ /* end node */ }
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};
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MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
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static int stm32_iwdg_irq_init(struct platform_device *pdev,
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struct stm32_iwdg *wdt)
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{
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struct device_node *np = pdev->dev.of_node;
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struct watchdog_device *wdd = &wdt->wdd;
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struct device *dev = &pdev->dev;
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int irq, ret;
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if (!wdt->data->has_early_wakeup)
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return 0;
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return 0;
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if (of_property_read_bool(np, "wakeup-source")) {
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ret = device_init_wakeup(dev, true);
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if (ret)
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return ret;
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ret = dev_pm_set_wake_irq(dev, irq);
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if (ret)
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return ret;
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}
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ret = devm_request_irq(dev, irq, stm32_iwdg_isr, 0,
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dev_name(dev), wdd);
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if (ret)
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return ret;
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wdd->info = &stm32_iwdg_preinfo;
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return 0;
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}
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static int stm32_iwdg_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct watchdog_device *wdd;
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struct stm32_iwdg *wdt;
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int ret;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->data = of_device_get_match_data(&pdev->dev);
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if (!wdt->data)
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return -ENODEV;
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/* This is the timer base. */
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wdt->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(wdt->regs))
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return PTR_ERR(wdt->regs);
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ret = stm32_iwdg_clk_init(pdev, wdt);
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if (ret)
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return ret;
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/* Initialize struct watchdog_device. */
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wdd = &wdt->wdd;
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wdd->parent = dev;
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wdd->info = &stm32_iwdg_info;
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wdd->ops = &stm32_iwdg_ops;
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wdd->timeout = DEFAULT_TIMEOUT;
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wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
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wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
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1000) / wdt->rate;
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/* Initialize IRQ, this might override wdd->info, hence it is here. */
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ret = stm32_iwdg_irq_init(pdev, wdt);
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if (ret)
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return ret;
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watchdog_set_drvdata(wdd, wdt);
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watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
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watchdog_init_timeout(wdd, 0, dev);
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/*
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* In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
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* (Means U-Boot/bootloaders leaves the watchdog running)
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* When we get here we should make a decision to prevent
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* any side effects before user space daemon will take care of it.
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* The best option, taking into consideration that there is no
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* way to read values back from hardware, is to enforce watchdog
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* being run with deterministic values.
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*/
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if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
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ret = stm32_iwdg_start(wdd);
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if (ret)
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return ret;
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/* Make sure the watchdog is serviced */
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set_bit(WDOG_HW_RUNNING, &wdd->status);
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}
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ret = devm_watchdog_register_device(dev, wdd);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, wdt);
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return 0;
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}
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static struct platform_driver stm32_iwdg_driver = {
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.probe = stm32_iwdg_probe,
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.driver = {
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.name = "iwdg",
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.of_match_table = stm32_iwdg_of_match,
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},
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};
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module_platform_driver(stm32_iwdg_driver);
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MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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