Rob Herring (Arm) 0bbff9ed81 perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control ...

Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter
access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual
counters are enabled/disabled in the PMUACR_EL1 register. When UEN is
set, the CR/ER bits control EL0 write access and must be set to disable
write access.

With the access controls, the clearing of unused counters can be
skipped.

KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not
need to be set for it since only PMUv3.5 is exposed to guests.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

2024-10-28 17:27:15 +00:00

..

arm_pmu.h

perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter

2024-08-16 13:09:12 +01:00

arm_pmuv3.h

perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control

2024-10-28 17:27:15 +00:00

riscv_pmu.h

drivers/perf: riscv: Implement SBI PMU snapshot function

2024-04-26 13:13:16 +05:30