Marc Zyngier 11af4c3716 KVM: arm64: PMU: Implement PMUv3p5 long counter support ...

PMUv3p5 (which is mandatory with ARMv8.5) comes with some extra
features:

- All counters are 64bit

- The overflow point is controlled by the PMCR_EL0.LP bit

Add the required checks in the helpers that control counter
width and overflow, as well as the sysreg handling for the LP
bit. A new kvm_pmu_is_3p5() helper makes it easy to spot the
PMUv3p5 specific handling.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221113163832.3154370-14-maz@kernel.org

2022-11-19 12:56:39 +00:00

..

arm_arch_timer.h

KVM: arm64: Simplify kvm_cpu_has_pending_timer()

2022-04-20 13:24:44 +01:00

arm_hypercalls.h

KVM: arm64: Setup a framework for hypercall bitmap firmware registers

2022-05-03 21:30:19 +01:00

arm_pmu.h

KVM: arm64: PMU: Implement PMUv3p5 long counter support

2022-11-19 12:56:39 +00:00

arm_psci.h

KVM: arm64: Factor out firmware register handling from psci.c

2022-05-03 14:48:54 +01:00

arm_vgic.h

KVM: arm64: vgic: Consolidate userspace access for base address setting

2022-07-17 11:55:33 +01:00

iodev.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 342

2019-06-05 17:37:07 +02:00