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ad5d960168
The DTS code coding style expects spaces around '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #display/msm Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230702182308.7583-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
55 lines
1.3 KiB
YAML
55 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic G12 DDR performance monitor
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maintainers:
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- Jiucheng Xu <jiucheng.xu@amlogic.com>
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description: |
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Amlogic G12 series SoC integrate DDR bandwidth monitor.
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A timer is inside and can generate interrupt when timeout.
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The bandwidth is counted in the timer ISR. Different platform
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has different subset of event format attribute.
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properties:
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compatible:
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enum:
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- amlogic,g12a-ddr-pmu
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- amlogic,g12b-ddr-pmu
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- amlogic,sm1-ddr-pmu
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reg:
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items:
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- description: DMC bandwidth register space.
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- description: DMC PLL register space.
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interrupts:
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items:
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- description: The IRQ of the inside timer timeout.
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pmu {
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#address-cells = <2>;
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#size-cells = <2>;
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pmu@ff638000 {
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compatible = "amlogic,g12a-ddr-pmu";
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reg = <0x0 0xff638000 0x0 0x100>,
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<0x0 0xff638c00 0x0 0x100>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
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};
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};
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