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38737d82f9
MSI-X vector Mask Bits are in MSI-X Tables in PCI memory space. Xen PV
guests can't write to those tables. MSI vector Mask Bits are in PCI
configuration space. Xen PV guests can write to config space, but those
writes are ignored.
Commit 0e4ccb1505a9 ("PCI: Add x86_msi.msi_mask_irq() and
msix_mask_irq()") added a way to override default_mask_msi_irqs() and
default_mask_msix_irqs() so they can be no-ops in Xen guests, but this is
more complicated than necessary.
Add "pci_msi_ignore_mask" in the core PCI MSI code. If set,
default_mask_msi_irqs() and default_mask_msix_irqs() return without doing
anything. This is less flexible, but much simpler.
[bhelgaas: changelog]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: David Vrabel <david.vrabel@citrix.com>
CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
CC: xen-devel@lists.xenproject.org
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
#ifndef LINUX_MSI_H
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#define LINUX_MSI_H
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#include <linux/kobject.h>
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#include <linux/list.h>
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struct msi_msg {
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u32 address_lo; /* low 32 bits of msi message address */
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u32 address_hi; /* high 32 bits of msi message address */
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u32 data; /* 16 bits of msi message data */
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};
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extern int pci_msi_ignore_mask;
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/* Helper functions */
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struct irq_data;
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struct msi_desc;
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void mask_msi_irq(struct irq_data *data);
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void unmask_msi_irq(struct irq_data *data);
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void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
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void read_msi_msg(unsigned int irq, struct msi_msg *msg);
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void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
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void write_msi_msg(unsigned int irq, struct msi_msg *msg);
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struct msi_desc {
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struct {
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__u8 is_msix : 1;
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__u8 multiple: 3; /* log2 num of messages allocated */
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__u8 multi_cap : 3; /* log2 num of messages supported */
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
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__u16 entry_nr; /* specific enabled entry */
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unsigned default_irq; /* default pre-assigned irq */
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} msi_attrib;
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u32 masked; /* mask bits */
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unsigned int irq;
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unsigned int nvec_used; /* number of messages */
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struct list_head list;
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union {
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void __iomem *mask_base;
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u8 mask_pos;
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};
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struct pci_dev *dev;
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/* Last set MSI message */
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struct msi_msg msg;
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};
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/*
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* The arch hooks to setup up msi irqs. Those functions are
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* implemented as weak symbols so that they /can/ be overriden by
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* architecture specific code if needed.
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*/
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int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
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void arch_teardown_msi_irq(unsigned int irq);
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int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
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void arch_teardown_msi_irqs(struct pci_dev *dev);
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void arch_restore_msi_irqs(struct pci_dev *dev);
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void default_teardown_msi_irqs(struct pci_dev *dev);
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void default_restore_msi_irqs(struct pci_dev *dev);
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u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
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u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);
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struct msi_chip {
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struct module *owner;
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struct device *dev;
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struct device_node *of_node;
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struct list_head list;
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int (*setup_irq)(struct msi_chip *chip, struct pci_dev *dev,
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struct msi_desc *desc);
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void (*teardown_irq)(struct msi_chip *chip, unsigned int irq);
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};
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#endif /* LINUX_MSI_H */
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