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Both ACPI and DT provide the ability to describe additional layers of
topology between that of individual cores and higher level constructs
such as the level at which the last level cache is shared.
In ACPI this can be represented in PPTT as a Processor Hierarchy
Node Structure [1] that is the parent of the CPU cores and in turn
has a parent Processor Hierarchy Nodes Structure representing
a higher level of topology.
For example Kunpeng 920 has 6 or 8 clusters in each NUMA node, and each
cluster has 4 cpus. All clusters share L3 cache data, but each cluster
has local L3 tag. On the other hand, each clusters will share some
internal system bus.
+-----------------------------------+ +---------+
| +------+ +------+ +--------------------------+ |
| | CPU0 | | cpu1 | | +-----------+ | |
| +------+ +------+ | | | | |
| +----+ L3 | | |
| +------+ +------+ cluster | | tag | | |
| | CPU2 | | CPU3 | | | | | |
| +------+ +------+ | +-----------+ | |
| | | |
+-----------------------------------+ | |
+-----------------------------------+ | |
| +------+ +------+ +--------------------------+ |
| | | | | | +-----------+ | |
| +------+ +------+ | | | | |
| | | L3 | | |
| +------+ +------+ +----+ tag | | |
| | | | | | | | | |
| +------+ +------+ | +-----------+ | |
| | | |
+-----------------------------------+ | L3 |
| data |
+-----------------------------------+ | |
| +------+ +------+ | +-----------+ | |
| | | | | | | | | |
| +------+ +------+ +----+ L3 | | |
| | | tag | | |
| +------+ +------+ | | | | |
| | | | | | +-----------+ | |
| +------+ +------+ +--------------------------+ |
+-----------------------------------| | |
+-----------------------------------| | |
| +------+ +------+ +--------------------------+ |
| | | | | | +-----------+ | |
| +------+ +------+ | | | | |
| +----+ L3 | | |
| +------+ +------+ | | tag | | |
| | | | | | | | | |
| +------+ +------+ | +-----------+ | |
| | | |
+-----------------------------------+ | |
+-----------------------------------+ | |
| +------+ +------+ +--------------------------+ |
| | | | | | +-----------+ | |
| +------+ +------+ | | | | |
| | | L3 | | |
| +------+ +------+ +---+ tag | | |
| | | | | | | | | |
| +------+ +------+ | +-----------+ | |
| | | |
+-----------------------------------+ | |
+-----------------------------------+ | |
| +------+ +------+ +--------------------------+ |
| | | | | | +-----------+ | |
| +------+ +------+ | | | | |
| | | L3 | | |
| +------+ +------+ +--+ tag | | |
| | | | | | | | | |
| +------+ +------+ | +-----------+ | |
| | +---------+
+-----------------------------------+
That means spreading tasks among clusters will bring more bandwidth
while packing tasks within one cluster will lead to smaller cache
synchronization latency. So both kernel and userspace will have
a chance to leverage this topology to deploy tasks accordingly to
achieve either smaller cache latency within one cluster or an even
distribution of load among clusters for higher throughput.
This patch exposes cluster topology to both kernel and userspace.
Libraried like hwloc will know cluster by cluster_cpus and related
sysfs attributes. PoC of HWLOC support at [2].
Note this patch only handle the ACPI case.
Special consideration is needed for SMT processors, where it is
necessary to move 2 levels up the hierarchy from the leaf nodes
(thus skipping the processor core level).
Note that arm64 / ACPI does not provide any means of identifying
a die level in the topology but that may be unrelate to the cluster
level.
[1] ACPI Specification 6.3 - section 5.2.29.1 processor hierarchy node
structure (Type 0)
[2] https://github.com/hisilicon/hwloc/tree/linux-cluster
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Barry Song <song.bao.hua@hisilicon.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210924085104.44806-2-21cnbao@gmail.com
95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* include/linux/arch_topology.h - arch specific cpu topology information
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*/
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#ifndef _LINUX_ARCH_TOPOLOGY_H_
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#define _LINUX_ARCH_TOPOLOGY_H_
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#include <linux/types.h>
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#include <linux/percpu.h>
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void topology_normalize_cpu_scale(void);
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int topology_update_cpu_topology(void);
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struct device_node;
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bool topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu);
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DECLARE_PER_CPU(unsigned long, cpu_scale);
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static inline unsigned long topology_get_cpu_scale(int cpu)
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{
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return per_cpu(cpu_scale, cpu);
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}
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void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity);
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DECLARE_PER_CPU(unsigned long, arch_freq_scale);
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static inline unsigned long topology_get_freq_scale(int cpu)
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{
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return per_cpu(arch_freq_scale, cpu);
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}
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void topology_set_freq_scale(const struct cpumask *cpus, unsigned long cur_freq,
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unsigned long max_freq);
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bool topology_scale_freq_invariant(void);
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enum scale_freq_source {
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SCALE_FREQ_SOURCE_CPUFREQ = 0,
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SCALE_FREQ_SOURCE_ARCH,
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SCALE_FREQ_SOURCE_CPPC,
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};
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struct scale_freq_data {
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enum scale_freq_source source;
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void (*set_freq_scale)(void);
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};
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void topology_scale_freq_tick(void);
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void topology_set_scale_freq_source(struct scale_freq_data *data, const struct cpumask *cpus);
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void topology_clear_scale_freq_source(enum scale_freq_source source, const struct cpumask *cpus);
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DECLARE_PER_CPU(unsigned long, thermal_pressure);
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static inline unsigned long topology_get_thermal_pressure(int cpu)
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{
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return per_cpu(thermal_pressure, cpu);
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}
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void topology_set_thermal_pressure(const struct cpumask *cpus,
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unsigned long th_pressure);
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struct cpu_topology {
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int thread_id;
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int core_id;
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int cluster_id;
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int package_id;
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int llc_id;
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cpumask_t thread_sibling;
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cpumask_t core_sibling;
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cpumask_t cluster_sibling;
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cpumask_t llc_sibling;
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};
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#ifdef CONFIG_GENERIC_ARCH_TOPOLOGY
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extern struct cpu_topology cpu_topology[NR_CPUS];
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#define topology_physical_package_id(cpu) (cpu_topology[cpu].package_id)
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#define topology_cluster_id(cpu) (cpu_topology[cpu].cluster_id)
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#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
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#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
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#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
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#define topology_cluster_cpumask(cpu) (&cpu_topology[cpu].cluster_sibling)
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#define topology_llc_cpumask(cpu) (&cpu_topology[cpu].llc_sibling)
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void init_cpu_topology(void);
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void store_cpu_topology(unsigned int cpuid);
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const struct cpumask *cpu_coregroup_mask(int cpu);
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const struct cpumask *cpu_clustergroup_mask(int cpu);
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void update_siblings_masks(unsigned int cpu);
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void remove_cpu_topology(unsigned int cpuid);
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void reset_cpu_topology(void);
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int parse_acpi_topology(void);
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#endif
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#endif /* _LINUX_ARCH_TOPOLOGY_H_ */
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