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While CXL builds upon the PCI software model for enumeration and endpoint control, a static platform component is required to bootstrap the CXL memory layout. Similar to how ACPI identifies root-level PCI memory resources, ACPI data enumerates the address space and interleave configuration for CXL Memory. In addition to identifying host bridges, ACPI is responsible for enumerating the CXL memory space that can be addressed by downstream decoders. This is similar to the requirement for ACPI to publish resources via the _CRS method for PCI host bridges. Specifically, ACPI publishes a table, CXL Early Discovery Table (CEDT), which includes a list of CXL Memory resources, CXL Fixed Memory Window Structures (CFMWS). For now, introduce the core infrastructure for a cxl_port hierarchy starting with a root level anchor represented by the ACPI0017 device. Follow on changes model support for the configurable decode capabilities of cxl_port instances, i.e. CXL switch support. Co-developed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Alison Schofield <alison.schofield@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162325449515.2293126.15303270193010154608.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
64 lines
2.5 KiB
Plaintext
64 lines
2.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menuconfig CXL_BUS
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tristate "CXL (Compute Express Link) Devices Support"
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depends on PCI
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help
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CXL is a bus that is electrically compatible with PCI Express, but
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layers three protocols on that signalling (CXL.io, CXL.cache, and
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CXL.mem). The CXL.cache protocol allows devices to hold cachelines
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locally, the CXL.mem protocol allows devices to be fully coherent
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memory targets, the CXL.io protocol is equivalent to PCI Express.
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Say 'y' to enable support for the configuration and management of
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devices supporting these protocols.
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if CXL_BUS
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config CXL_MEM
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tristate "CXL.mem: Memory Devices"
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help
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The CXL.mem protocol allows a device to act as a provider of
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"System RAM" and/or "Persistent Memory" that is fully coherent
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as if the memory was attached to the typical CPU memory
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controller.
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Say 'y/m' to enable a driver that will attach to CXL.mem devices for
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configuration and management primarily via the mailbox interface. See
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Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
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details.
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If unsure say 'm'.
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config CXL_MEM_RAW_COMMANDS
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bool "RAW Command Interface for Memory Devices"
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depends on CXL_MEM
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help
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Enable CXL RAW command interface.
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The CXL driver ioctl interface may assign a kernel ioctl command
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number for each specification defined opcode. At any given point in
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time the number of opcodes that the specification defines and a device
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may implement may exceed the kernel's set of associated ioctl function
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numbers. The mismatch is either by omission, specification is too new,
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or by design. When prototyping new hardware, or developing / debugging
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the driver it is useful to be able to submit any possible command to
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the hardware, even commands that may crash the kernel due to their
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potential impact to memory currently in use by the kernel.
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If developing CXL hardware or the driver say Y, otherwise say N.
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config CXL_ACPI
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tristate "CXL ACPI: Platform Support"
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depends on ACPI
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help
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Enable support for host managed device memory (HDM) resources
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published by a platform's ACPI CXL memory layout description. See
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Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
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specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
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(https://www.computeexpresslink.org/spec-landing). The CXL core
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consumes these resource to publish the root of a cxl_port decode
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hierarchy to map regions that represent System RAM, or Persistent
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Memory regions to be managed by LIBNVDIMM.
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If unsure say 'm'.
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endif
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