Dave Jiang 4d07a05397 cxl: Calculate and store PCI link latency for the downstream ports ... The latency is calculated by dividing the flit size over the bandwidth. Add support to retrieve the flit size for the CXL switch device and calculate the latency of the PCIe link. Cache the latency number with cxl_dport. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/170319621931.2212653.6800240203604822886.stgit@djiang5-mobl3 Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-12-22 14:53:49 -08:00
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core	cxl: Calculate and store PCI link latency for the downstream ports	2023-12-22 14:53:49 -08:00
acpi.c	cxl: Add support for _DSM Function for retrieving QTG ID	2023-12-22 14:33:28 -08:00
cxl.h	cxl: Calculate and store PCI link latency for the downstream ports	2023-12-22 14:53:49 -08:00
cxlmem.h	Merge branch 'for-6.7/cxl-rch-eh' into cxl/next	2023-10-31 10:59:00 -07:00
cxlpci.h	cxl: Calculate and store PCI link latency for the downstream ports	2023-12-22 14:53:49 -08:00
Kconfig	cxl: Add callback to parse the DSMAS subtables from CDAT	2023-12-22 14:33:10 -08:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
mem.c	cxl/pci: Add RCH downstream port AER register discovery	2023-10-27 20:13:38 -07:00
pci.c	Merge branch 'for-6.7/cxl' into cxl/next	2023-10-31 10:59:44 -07:00
pmem.c	cxl/mbox: Move mailbox related driver state to its own data structure	2023-06-25 14:31:08 -07:00
pmu.h	cxl/pci: Find and register CXL PMU devices	2023-05-30 11:20:35 -07:00
port.c	cxl: Add callback to parse the SSLBIS subtable from CDAT	2023-12-22 14:33:28 -08:00
security.c	Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl	2023-06-25 17:16:51 -07:00