Rajan Vaja 4ebd92d2e2 clk: zynqmp: Fix divider calculation ...

zynqmp_clk_divider_round_rate() returns actual divider value
after calculating from parent rate and desired rate, even though
that rate is not supported by single divider of hardware. It is
also possible that such divisor value can be achieved through 2
different dividers. As, Linux tries to set such divisor value(out
of range) in single divider set divider is getting failed.

Fix the same by computing best possible combination of two
divisors which provides more accurate clock rate.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lkml.kernel.org/r/1575527759-26452-6-git-send-email-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2020-01-23 13:25:37 -08:00

..

clk-gate-zynqmp.c

drivers: clk: Add ZynqMP clock driver

2018-10-09 13:29:19 +02:00

clk-mux-zynqmp.c

clk: zynqmp: do not export zynqmp_clk_register_* functions

2019-04-11 11:33:11 -07:00

clk-zynqmp.h

clk: zynqmp: use structs for clk query responses

2019-04-19 13:59:55 -07:00

clkc.c

clk: zynqmp: Extend driver for versal

2020-01-23 13:22:44 -08:00

divider.c

clk: zynqmp: Fix divider calculation

2020-01-23 13:25:37 -08:00

Kconfig

drivers: clk: Add ZynqMP clock driver

2018-10-09 13:29:19 +02:00

Makefile

drivers: clk: Add ZynqMP clock driver

2018-10-09 13:29:19 +02:00

pll.c

clk: zynqmp: Warn user if clock user are more than allowed

2020-01-23 13:25:25 -08:00