Jeeja KP 5518af9f97 ASoC: Intel: bxtn: Disable interrupt when DSP is in D3
When DSP is in D3, no interrupts are expected, so disable
interrupt while entering D3.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-03-15 17:27:58 +00:00
..
2016-10-07 20:19:31 -07:00
2017-01-24 16:24:18 +00:00
2017-03-01 09:59:21 -08:00
2017-02-27 18:43:47 -08:00
2016-12-25 17:21:22 +01:00
2016-01-20 09:59:27 +01:00
2015-08-31 16:25:22 +02:00