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a6a70a670c
Add support for customized parent indices for MediaTek muxes: this is necessary for the case in which we want to exclude some clocks from a mux's parent clocks list, where the exclusions are not from the very bottom of the list but either in the middle or the beginning. Example: - MUX1 (all parents) - parent1; idx=0 - parent2; idx=1 - parent3; idx=2 - MUX1 (wanted parents) - parent1; idx=0 - parent3; idx=2 To achieve that add a `parent_index` array pointer to struct mtk_mux, then in .set_parent(), .get_parent() callbacks check if this array was populated and eventually get the index from that. Also, to avoid updating all clock drivers for all SoCs, rename the "main" macro to __GATE_CLR_SET_UPD_FLAGS (so, `__` was added) and add the new member to it; furthermore, GATE_CLK_SET_UPD_FLAGS has been reintroduced as being fully compatible with the older version. The new parent_index can be specified with the new `_INDEXED` variants of the MUX_GATE_CLR_SET_UPD_xxxx macros. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-2-angelogioacchino.delregno@collabora.com Tested-by: Fei Shao <fshao@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
144 lines
4.4 KiB
C
144 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_MUX_H
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#define __DRV_CLK_MTK_MUX_H
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#include <linux/notifier.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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struct clk;
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struct clk_hw_onecell_data;
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struct clk_ops;
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struct device;
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struct device_node;
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struct mtk_mux {
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int id;
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const char *name;
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const char * const *parent_names;
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const u8 *parent_index;
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unsigned int flags;
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u32 mux_ofs;
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u32 set_ofs;
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u32 clr_ofs;
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u32 upd_ofs;
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u8 mux_shift;
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u8 mux_width;
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u8 gate_shift;
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s8 upd_shift;
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const struct clk_ops *ops;
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signed char num_parents;
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};
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#define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
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_num_parents, _mux_ofs, _mux_set_ofs, \
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_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \
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_upd, _flags, _ops) { \
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.id = _id, \
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.name = _name, \
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.mux_ofs = _mux_ofs, \
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.set_ofs = _mux_set_ofs, \
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.clr_ofs = _mux_clr_ofs, \
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.upd_ofs = _upd_ofs, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = _gate, \
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.upd_shift = _upd, \
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.parent_names = _parents, \
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.parent_index = _paridx, \
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.num_parents = _num_parents, \
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.flags = _flags, \
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.ops = &_ops, \
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}
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#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, _ops) \
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__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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NULL, ARRAY_SIZE(_parents), _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, _ops) \
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#define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd, _flags, _ops) \
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__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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_paridx, ARRAY_SIZE(_paridx), _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, _ops) \
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extern const struct clk_ops mtk_mux_clr_set_upd_ops;
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extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
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#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags) \
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GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, \
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mtk_mux_gate_clr_set_upd_ops)
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#define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
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_paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
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_shift, _width, _gate, _upd_ofs, _upd, _flags) \
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GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
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_paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
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_shift, _width, _gate, _upd_ofs, _upd, _flags, \
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mtk_mux_gate_clr_set_upd_ops)
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#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd) \
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MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd, \
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CLK_SET_RATE_PARENT)
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#define MUX_GATE_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd) \
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MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, \
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_parents, _paridx, _mux_ofs, _mux_set_ofs, \
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_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \
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_upd, CLK_SET_RATE_PARENT)
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#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_upd_ofs, _upd) \
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GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
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mtk_mux_clr_set_upd_ops)
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int mtk_clk_register_muxes(struct device *dev,
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const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
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struct clk_hw_onecell_data *clk_data);
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struct mtk_mux_nb {
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struct notifier_block nb;
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const struct clk_ops *ops;
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u8 bypass_index; /* Which parent to temporarily use */
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u8 original_index; /* Set by notifier callback */
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};
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#define to_mtk_mux_nb(_nb) container_of(_nb, struct mtk_mux_nb, nb)
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int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk,
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struct mtk_mux_nb *mux_nb);
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#endif /* __DRV_CLK_MTK_MUX_H */
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