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f6ca3fb697
Both the JEDEC and ONFI specification say that read cache sequential
support is an optional command. This means that we not only need to
check whether the individual controller supports the command, we also
need to check the parameter pages for both ONFI and JEDEC NAND flashes
before enabling sequential cache reads.
This fixes support for NAND flashes which don't support enabling cache
reads, i.e. Samsung K9F4G08U0F or Toshiba TC58NVG0S3HTA00.
Sequential cache reads are now only available for ONFI and JEDEC
devices, if individual vendors implement this, it needs to be enabled
per vendor.
Tested on i.MX6Q with a Samsung NAND flash chip that doesn't support
sequential reads.
Fixes:
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|---|---|---|
| .. | ||
| bbm.h | ||
| blktrans.h | ||
| cfi_endian.h | ||
| cfi.h | ||
| concat.h | ||
| doc2000.h | ||
| flashchip.h | ||
| ftl.h | ||
| gen_probe.h | ||
| hyperbus.h | ||
| inftl.h | ||
| jedec.h | ||
| lpc32xx_mlc.h | ||
| lpc32xx_slc.h | ||
| map.h | ||
| mtd.h | ||
| mtdram.h | ||
| nand-ecc-mtk.h | ||
| nand-ecc-mxic.h | ||
| nand-ecc-sw-bch.h | ||
| nand-ecc-sw-hamming.h | ||
| nand-gpio.h | ||
| nand.h | ||
| ndfc.h | ||
| nftl.h | ||
| onenand_regs.h | ||
| onenand.h | ||
| onfi.h | ||
| partitions.h | ||
| pfow.h | ||
| physmap.h | ||
| pismo.h | ||
| plat-ram.h | ||
| platnand.h | ||
| qinfo.h | ||
| rawnand.h | ||
| sh_flctl.h | ||
| sharpsl.h | ||
| spear_smi.h | ||
| spi-nor.h | ||
| spinand.h | ||
| super.h | ||
| ubi.h | ||
| xip.h | ||