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5e22bfd520
This function used to simply flush the whole tlb of all harts, be more subtile and try to only flush the range. The problem is that we can only use PAGE_SIZE as stride since we don't know the size of the underlying mapping and then this function will be improved only if the size of the region to flush is < threshold * PAGE_SIZE. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # On RZ/Five SMARC Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20231030133027.19542-5-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
203 lines
4.6 KiB
C
203 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/sched.h>
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#include <linux/hugetlb.h>
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#include <asm/sbi.h>
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#include <asm/mmu_context.h>
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static inline void local_flush_tlb_all_asid(unsigned long asid)
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{
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if (asid != FLUSH_TLB_NO_ASID)
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__asm__ __volatile__ ("sfence.vma x0, %0"
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:
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: "r" (asid)
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: "memory");
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else
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local_flush_tlb_all();
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}
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static inline void local_flush_tlb_page_asid(unsigned long addr,
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unsigned long asid)
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{
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if (asid != FLUSH_TLB_NO_ASID)
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__asm__ __volatile__ ("sfence.vma %0, %1"
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:
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: "r" (addr), "r" (asid)
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: "memory");
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else
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local_flush_tlb_page(addr);
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}
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/*
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* Flush entire TLB if number of entries to be flushed is greater
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* than the threshold below.
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*/
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static unsigned long tlb_flush_all_threshold __read_mostly = 64;
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static void local_flush_tlb_range_threshold_asid(unsigned long start,
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unsigned long size,
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unsigned long stride,
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unsigned long asid)
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{
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unsigned long nr_ptes_in_range = DIV_ROUND_UP(size, stride);
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int i;
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if (nr_ptes_in_range > tlb_flush_all_threshold) {
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local_flush_tlb_all_asid(asid);
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return;
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}
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for (i = 0; i < nr_ptes_in_range; ++i) {
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local_flush_tlb_page_asid(start, asid);
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start += stride;
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}
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}
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static inline void local_flush_tlb_range_asid(unsigned long start,
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unsigned long size, unsigned long stride, unsigned long asid)
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{
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if (size <= stride)
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local_flush_tlb_page_asid(start, asid);
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else if (size == FLUSH_TLB_MAX_SIZE)
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local_flush_tlb_all_asid(asid);
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else
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local_flush_tlb_range_threshold_asid(start, size, stride, asid);
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}
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static void __ipi_flush_tlb_all(void *info)
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{
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local_flush_tlb_all();
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}
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void flush_tlb_all(void)
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{
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if (riscv_use_ipi_for_rfence())
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on_each_cpu(__ipi_flush_tlb_all, NULL, 1);
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else
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sbi_remote_sfence_vma_asid(NULL, 0, FLUSH_TLB_MAX_SIZE, FLUSH_TLB_NO_ASID);
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}
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struct flush_tlb_range_data {
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unsigned long asid;
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unsigned long start;
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unsigned long size;
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unsigned long stride;
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};
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static void __ipi_flush_tlb_range_asid(void *info)
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{
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struct flush_tlb_range_data *d = info;
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local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
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}
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static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
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unsigned long size, unsigned long stride)
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{
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struct flush_tlb_range_data ftd;
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const struct cpumask *cmask;
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unsigned long asid = FLUSH_TLB_NO_ASID;
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bool broadcast;
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if (mm) {
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unsigned int cpuid;
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cmask = mm_cpumask(mm);
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if (cpumask_empty(cmask))
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return;
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cpuid = get_cpu();
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/* check if the tlbflush needs to be sent to other CPUs */
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broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
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if (static_branch_unlikely(&use_asid_allocator))
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asid = atomic_long_read(&mm->context.id) & asid_mask;
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} else {
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cmask = cpu_online_mask;
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broadcast = true;
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}
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if (broadcast) {
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if (riscv_use_ipi_for_rfence()) {
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ftd.asid = asid;
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ftd.start = start;
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ftd.size = size;
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ftd.stride = stride;
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on_each_cpu_mask(cmask,
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__ipi_flush_tlb_range_asid,
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&ftd, 1);
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} else
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sbi_remote_sfence_vma_asid(cmask,
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start, size, asid);
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} else {
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local_flush_tlb_range_asid(start, size, stride, asid);
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}
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if (mm)
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put_cpu();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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__flush_tlb_range(mm, 0, FLUSH_TLB_MAX_SIZE, PAGE_SIZE);
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}
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void flush_tlb_mm_range(struct mm_struct *mm,
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unsigned long start, unsigned long end,
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unsigned int page_size)
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{
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__flush_tlb_range(mm, start, end - start, page_size);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
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{
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__flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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unsigned long stride_size;
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if (!is_vm_hugetlb_page(vma)) {
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stride_size = PAGE_SIZE;
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} else {
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stride_size = huge_page_size(hstate_vma(vma));
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/*
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* As stated in the privileged specification, every PTE in a
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* NAPOT region must be invalidated, so reset the stride in that
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* case.
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*/
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if (has_svnapot()) {
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if (stride_size >= PGDIR_SIZE)
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stride_size = PGDIR_SIZE;
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else if (stride_size >= P4D_SIZE)
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stride_size = P4D_SIZE;
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else if (stride_size >= PUD_SIZE)
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stride_size = PUD_SIZE;
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else if (stride_size >= PMD_SIZE)
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stride_size = PMD_SIZE;
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else
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stride_size = PAGE_SIZE;
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}
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}
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__flush_tlb_range(vma->vm_mm, start, end - start, stride_size);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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__flush_tlb_range(NULL, start, end - start, PAGE_SIZE);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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__flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE);
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}
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#endif
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