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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 94 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141334.043630402@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Hexagon VM page table entry definitions
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*
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* Copyright (c) 2010-2011,2013 The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_VM_MMU_H
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#define _ASM_VM_MMU_H
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/*
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* Shift, mask, and other constants for the Hexagon Virtual Machine
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* page tables.
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*
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* Virtual machine MMU allows first-level entries to either be
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* single-level lookup PTEs for very large pages, or PDEs pointing
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* to second-level PTEs for smaller pages. If PTE is single-level,
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* the least significant bits cannot be used as software bits to encode
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* virtual memory subsystem information about the page, and that state
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* must be maintained in some parallel data structure.
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*/
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/* S or Page Size field in PDE */
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#define __HVM_PDE_S (0x7 << 0)
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#define __HVM_PDE_S_4KB 0
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#define __HVM_PDE_S_16KB 1
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#define __HVM_PDE_S_64KB 2
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#define __HVM_PDE_S_256KB 3
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#define __HVM_PDE_S_1MB 4
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#define __HVM_PDE_S_4MB 5
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#define __HVM_PDE_S_16MB 6
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#define __HVM_PDE_S_INVALID 7
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/* Masks for L2 page table pointer, as function of page size */
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#define __HVM_PDE_PTMASK_4KB 0xfffff000
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#define __HVM_PDE_PTMASK_16KB 0xfffffc00
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#define __HVM_PDE_PTMASK_64KB 0xffffff00
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#define __HVM_PDE_PTMASK_256KB 0xffffffc0
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#define __HVM_PDE_PTMASK_1MB 0xfffffff0
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/*
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* Virtual Machine PTE Bits/Fields
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*/
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#define __HVM_PTE_T (1<<4)
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#define __HVM_PTE_U (1<<5)
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#define __HVM_PTE_C (0x7<<6)
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#define __HVM_PTE_CVAL(pte) (((pte) & __HVM_PTE_C) >> 6)
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#define __HVM_PTE_R (1<<9)
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#define __HVM_PTE_W (1<<10)
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#define __HVM_PTE_X (1<<11)
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/*
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* Cache Attributes, to be shifted as necessary for virtual/physical PTEs
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*/
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#define __HEXAGON_C_WB 0x0 /* Write-back, no L2 */
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#define __HEXAGON_C_WT 0x1 /* Write-through, no L2 */
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#define __HEXAGON_C_UNC 0x6 /* Uncached memory */
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#if CONFIG_HEXAGON_ARCH_VERSION >= 2
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#define __HEXAGON_C_DEV 0x4 /* Device register space */
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#else
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#define __HEXAGON_C_DEV __HEXAGON_C_UNC
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#endif
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#define __HEXAGON_C_WT_L2 0x5 /* Write-through, with L2 */
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#define __HEXAGON_C_WB_L2 0x7 /* Write-back, with L2 */
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/*
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* This can be overridden, but we're defaulting to the most aggressive
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* cache policy, the better to find bugs sooner.
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*/
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#define CACHE_DEFAULT __HEXAGON_C_WB_L2
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/* Masks for physical page address, as a function of page size */
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#define __HVM_PTE_PGMASK_4KB 0xfffff000
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#define __HVM_PTE_PGMASK_16KB 0xffffc000
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#define __HVM_PTE_PGMASK_64KB 0xffff0000
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#define __HVM_PTE_PGMASK_256KB 0xfffc0000
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#define __HVM_PTE_PGMASK_1MB 0xfff00000
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/* Masks for single-level large page lookups */
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#define __HVM_PTE_PGMASK_4MB 0xffc00000
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#define __HVM_PTE_PGMASK_16MB 0xff000000
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/*
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* "Big kernel page mappings" (see vm_init_segtable.S)
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* are currently 16MB
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*/
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#define BIG_KERNEL_PAGE_SHIFT 24
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#define BIG_KERNEL_PAGE_SIZE (1 << BIG_KERNEL_PAGE_SHIFT)
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#endif /* _ASM_VM_MMU_H */
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