Athira Rajeev 65156f2b1d powerpc/perf: Initialize power10 PMU registers in cpu setup routine
Initialize Monitor Mode Control Register 3 (MMCR3)
SPR which is new in power10. For PowerISA v3.1, BHRB disable
is controlled via Monitor Mode Control Register A (MMCRA) bit,
namely "BHRB Recording Disable (BHRBRD)". This patch also initializes
MMCRA BHRBRD to disable BHRB feature at boot for power10.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1595489557-2047-1-git-send-email-atrajeev@linux.vnet.ibm.com
2020-07-26 23:34:23 +10:00
..
2020-05-14 16:44:25 +02:00
2019-09-20 11:48:06 -07:00
2020-03-10 15:16:42 +11:00
2019-08-30 09:52:57 +10:00
2020-07-26 23:34:20 +10:00
2020-06-05 12:39:30 -07:00
2020-05-26 23:36:57 +10:00
2020-07-18 22:43:55 +10:00
2020-06-05 12:39:30 -07:00
2020-04-05 11:12:59 -07:00
2020-07-23 17:43:44 +10:00
2020-05-26 23:36:51 +10:00
2020-07-16 13:12:47 +10:00
2020-06-05 12:39:30 -07:00