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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-12-29 09:16:33 +00:00
9f3a2ba62c
some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmc/r1kRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSUlaw/+NkmTMPSpgKy8NfZi6KoCk3U5llaknXvj Y/Y2pB7UpOFDTsSCKRcFrZ6JWS6GIogE70W9w+zxIht4QA4Ekd9vKT7VRhMl+8t/ pz2i0c0Pm24hSye9LKM7JCVIVL8SNYonOs3wC1sfMVMDoUikVwupj6Bmj0nAYrBo hbJFBXtn/LbyYImJQ9hYqHnUtJKGp/N7hhpGu6kT/lbzcaWsBMp4lhH+s20DJz5e kdJVJGaLOELerAG/SHIxh9obtfznvex6x3itTB0o/d6/1DSDjjlxnZH8YV8eQWk0 kK+ORuewA+qCi3RiPReHCPBIfPI4HL0z3k5JFA5eI7eD4VZIis+YBOa/Y8bQR9bG wDg5qh5su0fdeWBUvkFB03igNoMdtH68iYd2q3YE0ka95FGulcyvbqoyxTJnjIxW 328PizYZV8LQ4+LGSdIFyp9f/SrjF0pAt7yTF8Dis3jq3ul/6ELX9G6OCNgtGKQz p0Hb01fKC4s7w48QI5OXQKfS382vS8G8a2NIwt2xxorc4+Dr2rjPvlDhErshCOAT nDEerIjGWr/0rQeTGxg+SLUx5ytq2aBkysg95/9WVe3b8kZeePiW9gEH4tgealY8 eHzFvbqXutlKer0xLOYiLd3hOeHhkCJNj48QS8jVXtRGGeLjZONw5F1mjTNskPpx 9jbKMcDjGyc= =FqLm -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework gained a clk provider helper, a clk consumer helper, and some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access clk: Fix invalid execution of clk_set_rate clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider clk: lan966x: make it selectable for ARCH_LAN969X clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one ... |
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.. | ||
actions | ||
analogbits | ||
at91 | ||
axis | ||
axs10x | ||
baikal-t1 | ||
bcm | ||
berlin | ||
davinci | ||
hisilicon | ||
imgtec | ||
imx | ||
ingenic | ||
keystone | ||
mediatek | ||
meson | ||
microchip | ||
mmp | ||
mstar | ||
mvebu | ||
mxs | ||
nuvoton | ||
nxp | ||
pistachio | ||
pxa | ||
qcom | ||
ralink | ||
renesas | ||
rockchip | ||
samsung | ||
sifive | ||
socfpga | ||
sophgo | ||
spear | ||
sprd | ||
st | ||
starfive | ||
stm32 | ||
sunxi | ||
sunxi-ng | ||
tegra | ||
thead | ||
ti | ||
uniphier | ||
ux500 | ||
versatile | ||
visconti | ||
x86 | ||
xilinx | ||
zynq | ||
zynqmp | ||
.kunitconfig | ||
clk_kunit_helpers.c | ||
clk_parent_data_test.h | ||
clk_test.c | ||
clk-apple-nco.c | ||
clk-asm9260.c | ||
clk-aspeed.c | ||
clk-aspeed.h | ||
clk-ast2600.c | ||
clk-axi-clkgen.c | ||
clk-axm5516.c | ||
clk-bd718x7.c | ||
clk-bm1880.c | ||
clk-bulk.c | ||
clk-cdce706.c | ||
clk-cdce925.c | ||
clk-clps711x.c | ||
clk-composite.c | ||
clk-conf.c | ||
clk-cs2000-cp.c | ||
clk-devres.c | ||
clk-divider.c | ||
clk-en7523.c | ||
clk-ep93xx.c | ||
clk-eyeq.c | ||
clk-fixed-factor.c | ||
clk-fixed-mmio.c | ||
clk-fixed-rate_test.c | ||
clk-fixed-rate_test.h | ||
clk-fixed-rate.c | ||
clk-fractional-divider_test.c | ||
clk-fractional-divider.c | ||
clk-fractional-divider.h | ||
clk-fsl-flexspi.c | ||
clk-fsl-sai.c | ||
clk-gate_test.c | ||
clk-gate.c | ||
clk-gemini.c | ||
clk-gpio.c | ||
clk-hi655x.c | ||
clk-highbank.c | ||
clk-hsdk-pll.c | ||
clk-k210.c | ||
clk-lan966x.c | ||
clk-lmk04832.c | ||
clk-lochnagar.c | ||
clk-loongson1.c | ||
clk-loongson2.c | ||
clk-max9485.c | ||
clk-max77686.c | ||
clk-milbeaut.c | ||
clk-moxart.c | ||
clk-multiplier.c | ||
clk-mux.c | ||
clk-nomadik.c | ||
clk-npcm7xx.c | ||
clk-npcm8xx.c | ||
clk-nspire.c | ||
clk-palmas.c | ||
clk-plldig.c | ||
clk-pwm.c | ||
clk-qoriq.c | ||
clk-renesas-pcie.c | ||
clk-rk808.c | ||
clk-s2mps11.c | ||
clk-scmi.c | ||
clk-scpi.c | ||
clk-si514.c | ||
clk-si521xx.c | ||
clk-si544.c | ||
clk-si570.c | ||
clk-si5341.c | ||
clk-si5351.c | ||
clk-si5351.h | ||
clk-sp7021.c | ||
clk-sparx5.c | ||
clk-stm32f4.c | ||
clk-stm32h7.c | ||
clk-tps68470.c | ||
clk-twl6040.c | ||
clk-twl.c | ||
clk-versaclock3.c | ||
clk-versaclock5.c | ||
clk-versaclock7.c | ||
clk-vt8500.c | ||
clk-wm831x.c | ||
clk-xgene.c | ||
clk.c | ||
clk.h | ||
clkdev.c | ||
Kconfig | ||
kunit_clk_assigned_rates_multiple_consumer.dtso | ||
kunit_clk_assigned_rates_multiple.dtso | ||
kunit_clk_assigned_rates_null_consumer.dtso | ||
kunit_clk_assigned_rates_null.dtso | ||
kunit_clk_assigned_rates_one_consumer.dtso | ||
kunit_clk_assigned_rates_one.dtso | ||
kunit_clk_assigned_rates_u64_multiple_consumer.dtso | ||
kunit_clk_assigned_rates_u64_multiple.dtso | ||
kunit_clk_assigned_rates_u64_one_consumer.dtso | ||
kunit_clk_assigned_rates_u64_one.dtso | ||
kunit_clk_assigned_rates_without_consumer.dtso | ||
kunit_clk_assigned_rates_without.dtso | ||
kunit_clk_assigned_rates_zero_consumer.dtso | ||
kunit_clk_assigned_rates_zero.dtso | ||
kunit_clk_assigned_rates.h | ||
kunit_clk_fixed_rate_test.dtso | ||
kunit_clk_parent_data_test.dtso | ||
Makefile |