mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-09 06:33:34 +00:00
2605e80d34
- Support for the Armv8.9 Permission Indirection Extensions. While this
feature doesn't add new functionality, it enables future support for
Guarded Control Stacks (GCS) and Permission Overlays.
- User-space support for the Armv8.8 memcpy/memset instructions.
- arm64 perf: support the HiSilicon SoC uncore PMU, Arm CMN sysfs
identifier, support for the NXP i.MX9 SoC DDRC PMU, fixes and
cleanups.
- Removal of superfluous ISBs on context switch (following retrospective
architecture tightening).
- Decode the ISS2 register during faults for additional information to
help with debugging.
- KPTI clean-up/simplification of the trampoline exit code.
- Addressing several -Wmissing-prototype warnings.
- Kselftest improvements for signal handling and ptrace.
- Fix TPIDR2_EL0 restoring on sigreturn
- Clean-up, robustness improvements of the module allocation code.
- More sysreg conversions to the automatic register/bitfields
generation.
- CPU capabilities handling cleanup.
- Arm documentation updates: ACPI, ptdump.
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
"Notable features are user-space support for the memcpy/memset
instructions and the permission indirection extension.
- Support for the Armv8.9 Permission Indirection Extensions. While
this feature doesn't add new functionality, it enables future
support for Guarded Control Stacks (GCS) and Permission Overlays
- User-space support for the Armv8.8 memcpy/memset instructions
- arm64 perf: support the HiSilicon SoC uncore PMU, Arm CMN sysfs
identifier, support for the NXP i.MX9 SoC DDRC PMU, fixes and
cleanups
- Removal of superfluous ISBs on context switch (following
retrospective architecture tightening)
- Decode the ISS2 register during faults for additional information
to help with debugging
- KPTI clean-up/simplification of the trampoline exit code
- Addressing several -Wmissing-prototype warnings
- Kselftest improvements for signal handling and ptrace
- Fix TPIDR2_EL0 restoring on sigreturn
- Clean-up, robustness improvements of the module allocation code
- More sysreg conversions to the automatic register/bitfields
generation
- CPU capabilities handling cleanup
- Arm documentation updates: ACPI, ptdump"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (124 commits)
kselftest/arm64: Add a test case for TPIDR2 restore
arm64/signal: Restore TPIDR2 register rather than memory state
arm64: alternatives: make clean_dcache_range_nopatch() noinstr-safe
Documentation/arm64: Add ptdump documentation
arm64: hibernate: remove WARN_ON in save_processor_state
kselftest/arm64: Log signal code and address for unexpected signals
docs: perf: Fix warning from 'make htmldocs' in hisi-pmu.rst
arm64/fpsimd: Exit streaming mode when flushing tasks
docs: perf: Add new description for HiSilicon UC PMU
drivers/perf: hisi: Add support for HiSilicon UC PMU driver
drivers/perf: hisi: Add support for HiSilicon H60PA and PAv3 PMU driver
perf: arm_cspmu: Add missing MODULE_DEVICE_TABLE
perf/arm-cmn: Add sysfs identifier
perf/arm-cmn: Revamp model detection
perf/arm_dmc620: Add cpumask
arm64: mm: fix VA-range sanity check
arm64/mm: remove now-superfluous ISBs from TTBR writes
Documentation/arm64: Update ACPI tables from BBR
Documentation/arm64: Update references in arm-acpi
Documentation/arm64: Update ARM and arch reference
...
70 lines
2.6 KiB
C
70 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016, Semihalf
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* Author: Tomasz Nowicki <tn@semihalf.com>
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*/
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#ifndef __ACPI_IORT_H__
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#define __ACPI_IORT_H__
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#include <linux/acpi.h>
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#include <linux/fwnode.h>
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#include <linux/irqdomain.h>
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#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
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#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
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/*
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* PMCG model identifiers for use in smmu pmu driver. Please note
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* that this is purely for the use of software and has nothing to
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* do with hardware or with IORT specification.
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*/
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#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
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int iort_register_domain_token(int trans_id, phys_addr_t base,
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struct fwnode_handle *fw_node);
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void iort_deregister_domain_token(int trans_id);
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struct fwnode_handle *iort_find_domain_token(int trans_id);
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int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
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#ifdef CONFIG_ACPI_IORT
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u32 iort_msi_map_id(struct device *dev, u32 id);
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struct irq_domain *iort_get_device_domain(struct device *dev, u32 id,
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enum irq_domain_bus_token bus_token);
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void acpi_configure_pmsi_domain(struct device *dev);
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void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode,
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struct list_head *head);
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void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode,
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struct list_head *head);
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/* IOMMU interface */
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int iort_dma_get_ranges(struct device *dev, u64 *size);
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int iort_iommu_configure_id(struct device *dev, const u32 *id_in);
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void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head);
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phys_addr_t acpi_iort_dma_get_max_cpu_address(void);
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#else
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static inline u32 iort_msi_map_id(struct device *dev, u32 id)
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{ return id; }
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static inline struct irq_domain *iort_get_device_domain(
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struct device *dev, u32 id, enum irq_domain_bus_token bus_token)
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{ return NULL; }
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static inline void acpi_configure_pmsi_domain(struct device *dev) { }
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static inline
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void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
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static inline
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void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
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/* IOMMU interface */
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static inline int iort_dma_get_ranges(struct device *dev, u64 *size)
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{ return -ENODEV; }
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static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in)
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{ return -ENODEV; }
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static inline
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void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head)
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{ }
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static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void)
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{ return PHYS_ADDR_MAX; }
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#endif
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#endif /* __ACPI_IORT_H__ */
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