Tejas Patel 34bbe03617 clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag ...

Existing clock divider functions is not checking for
base of divider. So, if any clock divider is power of 2
then clock rate calculation will be wrong.

Add support to calculate divider value for the clocks
with CLK_DIVIDER_POWER_OF_TWO flag.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lkml.kernel.org/r/1575527759-26452-7-git-send-email-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2020-01-23 13:25:37 -08:00

..

clk-gate-zynqmp.c

drivers: clk: Add ZynqMP clock driver

2018-10-09 13:29:19 +02:00

clk-mux-zynqmp.c

clk: zynqmp: do not export zynqmp_clk_register_* functions

2019-04-11 11:33:11 -07:00

clk-zynqmp.h

clk: zynqmp: use structs for clk query responses

2019-04-19 13:59:55 -07:00

clkc.c

clk: zynqmp: Extend driver for versal

2020-01-23 13:22:44 -08:00

divider.c

clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag

2020-01-23 13:25:37 -08:00

Kconfig

drivers: clk: Add ZynqMP clock driver

2018-10-09 13:29:19 +02:00

Makefile

drivers: clk: Add ZynqMP clock driver

2018-10-09 13:29:19 +02:00

pll.c

clk: zynqmp: Warn user if clock user are more than allowed

2020-01-23 13:25:25 -08:00