mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-01-09 14:43:16 +00:00
d46392bbf5
* Support for cbo.zero in userspace. * Support for CBOs on ACPI-based systems. * A handful of improvements for the T-Head cache flushing ops. * Support for software shadow call stacks. * Various cleanups and fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmVJAJoTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiWZrD/9ECV/0tuX5LbS56kA0ElkwiakyIVGu ZVuF26yGJ6w+XvwnHPhqKNVN0ReYR6s6CwH1WpHI5Du9QHZGQU3DKJ43dFMTP3Dn dQFli7QJ+tsNo1nre8NZWKj5Ac+Cu906F794qM0q0XrZmyb9DY3ojVYJAYy+dtoo /9gwbB7P0GLyDlURLn48oQyz36WQW3CkL5Jkfu+uYwnFe9DAFtfakIKq5mLlNuaH PgUk8pAVhSy2GdPOGFtnFFhdXMrTjpgxdo62ZIZC0lbsts26Dxp95oUygqMg51Iy ilaXkA2U1c1+gFQNpEove7BVZa5708Kaj6RLQ3/kAJblAzibszwQvIWlWOh7RVni 3GQAS7/0D0+0cjDwXdWaPIaFFzLfi3bDxRYkc7n59p6nOz+GrxnSNsRPQJGgYxeU oTtJfaqWKntm72iutiHmXgx/pvAxWOHpqDnSTlDdtjvgzXCplqBbxZFF/azj30o5 jplNW5YvdvD9fviYMAoGSOz03IwDeZF5rMlAhqu6vXlyD2//mID82yw/hBluIA3+ /hLo5QfTLiUGs9nnijxMcfoyusN6AXsJOxwYdAJCIuJOr78YUj0S974gd9KvJXma KedrwRVwW7KE7CwY1jhrWBsZEpzl8YrtpMDN47y4gRtDZN8XJMQ+lHqd+BHT/DUO TGUCYi5xvr6Vlw== =hKWl -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for cbo.zero in userspace - Support for CBOs on ACPI-based systems - A handful of improvements for the T-Head cache flushing ops - Support for software shadow call stacks - Various cleanups and fixes * tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (31 commits) RISC-V: hwprobe: Fix vDSO SIGSEGV riscv: configs: defconfig: Enable configs required for RZ/Five SoC riscv: errata: prefix T-Head mnemonics with th. riscv: put interrupt entries into .irqentry.text riscv: mm: Update the comment of CONFIG_PAGE_OFFSET riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause riscv/mm: Fix the comment for swap pte format RISC-V: clarify the QEMU workaround in ISA parser riscv: correct pt_level name via pgtable_l5/4_enabled RISC-V: Provide pgtable_l5_enabled on rv32 clocksource: timer-riscv: Increase rating of clock_event_device for Sstc clocksource: timer-riscv: Don't enable/disable timer interrupt lkdtm: Fix CFI_BACKWARD on RISC-V riscv: Use separate IRQ shadow call stacks riscv: Implement Shadow Call Stack riscv: Move global pointer loading to a macro riscv: Deduplicate IRQ stack switching riscv: VMAP_STACK overflow detection thread-safe RISC-V: cacheflush: Initialize CBO variables on ACPI systems RISC-V: ACPI: RHCT: Add function to get CBO block sizes ...
117 lines
2.3 KiB
C
117 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2012 Regents of the University of California
|
|
* Copyright (C) 2017 SiFive
|
|
* Copyright (C) 2018 Christoph Hellwig
|
|
*/
|
|
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irqchip.h>
|
|
#include <linux/irqdomain.h>
|
|
#include <linux/module.h>
|
|
#include <linux/scs.h>
|
|
#include <linux/seq_file.h>
|
|
#include <asm/sbi.h>
|
|
#include <asm/smp.h>
|
|
#include <asm/softirq_stack.h>
|
|
#include <asm/stacktrace.h>
|
|
|
|
static struct fwnode_handle *(*__get_intc_node)(void);
|
|
|
|
void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void))
|
|
{
|
|
__get_intc_node = fn;
|
|
}
|
|
|
|
struct fwnode_handle *riscv_get_intc_hwnode(void)
|
|
{
|
|
if (__get_intc_node)
|
|
return __get_intc_node();
|
|
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode);
|
|
|
|
#ifdef CONFIG_IRQ_STACKS
|
|
#include <asm/irq_stack.h>
|
|
|
|
DECLARE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
|
|
|
|
#ifdef CONFIG_SHADOW_CALL_STACK
|
|
DEFINE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
|
|
#endif
|
|
|
|
static void init_irq_scs(void)
|
|
{
|
|
int cpu;
|
|
|
|
if (!scs_is_enabled())
|
|
return;
|
|
|
|
for_each_possible_cpu(cpu)
|
|
per_cpu(irq_shadow_call_stack_ptr, cpu) =
|
|
scs_alloc(cpu_to_node(cpu));
|
|
}
|
|
|
|
DEFINE_PER_CPU(ulong *, irq_stack_ptr);
|
|
|
|
#ifdef CONFIG_VMAP_STACK
|
|
static void init_irq_stacks(void)
|
|
{
|
|
int cpu;
|
|
ulong *p;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
p = arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu));
|
|
per_cpu(irq_stack_ptr, cpu) = p;
|
|
}
|
|
}
|
|
#else
|
|
/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
|
|
DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack);
|
|
|
|
static void init_irq_stacks(void)
|
|
{
|
|
int cpu;
|
|
|
|
for_each_possible_cpu(cpu)
|
|
per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu);
|
|
}
|
|
#endif /* CONFIG_VMAP_STACK */
|
|
|
|
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
|
static void ___do_softirq(struct pt_regs *regs)
|
|
{
|
|
__do_softirq();
|
|
}
|
|
|
|
void do_softirq_own_stack(void)
|
|
{
|
|
if (on_thread_stack())
|
|
call_on_irq_stack(NULL, ___do_softirq);
|
|
else
|
|
__do_softirq();
|
|
}
|
|
#endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */
|
|
|
|
#else
|
|
static void init_irq_scs(void) {}
|
|
static void init_irq_stacks(void) {}
|
|
#endif /* CONFIG_IRQ_STACKS */
|
|
|
|
int arch_show_interrupts(struct seq_file *p, int prec)
|
|
{
|
|
show_ipi_stats(p, prec);
|
|
return 0;
|
|
}
|
|
|
|
void __init init_IRQ(void)
|
|
{
|
|
init_irq_scs();
|
|
init_irq_stacks();
|
|
irqchip_init();
|
|
if (!handle_arch_irq)
|
|
panic("No interrupt controller found.");
|
|
sbi_ipi_init();
|
|
}
|