Alison Schofield 8f55ada796 cxl: Remove defunct code calculating host bridge target positions ... The CXL Spec 3.1 Table 9-22 requires that the BIOS populate the CFMWS target list in interleave target order. This means the calculations the CXL driver added to determine positions when XOR math is in use, along with the entire XOR vs Modulo call back setup is not needed. A prior patch added a common method to verify positions. Remove the now unused code related to the cxl_calc_hb_fn. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://patch.msgid.link/2e2c32a2d0f1007e920b58712d15edad2e48d857.1719980933.git.alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>		2024-07-11 16:29:43 -07:00
..
core	cxl: Remove defunct code calculating host bridge target positions	2024-07-11 16:29:43 -07:00
acpi.c	cxl: Remove defunct code calculating host bridge target positions	2024-07-11 16:29:43 -07:00
cxl.h	cxl: Remove defunct code calculating host bridge target positions	2024-07-11 16:29:43 -07:00
cxlmem.h	cxl/mbox: Add Clear Log mailbox command	2024-04-30 08:48:10 -07:00
cxlpci.h	PCI/CXL: Move CXL Vendor ID to pci_ids.h	2024-05-08 13:18:33 -05:00
Kconfig	cxl: Fix use of phys_to_target_node() for x86	2024-04-30 10:43:48 -07:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
mem.c	cxl: Fix sysfs export of qos_class for memdev	2024-02-16 23:20:34 -08:00
pci.c	pci-v6.10-changes	2024-05-21 10:09:28 -07:00
pmem.c	cxl: Fix compile warning for cxl_security_ops extern	2024-04-30 10:43:48 -07:00
pmu.h	cxl/pci: Find and register CXL PMU devices	2023-05-30 11:20:35 -07:00
port.c	cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_probe()	2024-01-05 14:36:29 -08:00
security.c	Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl	2023-06-25 17:16:51 -07:00