Thomas Gleixner 449437778b clk: spear3xx: Set proper clock parent of uart1/2 ...

The uarts only work when the parent is ras_ahb_clk. The stale 3.5
based ST tree does this in the board file.

Add it to the clk init function. Not pretty, but the mess there is
amazing anyway.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2014-07-13 07:12:11 -07:00

..

clk-aux-synth.c

CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks

2012-11-21 11:45:45 -08:00

clk-frac-synth.c

clk: SPEAr: Staticize clk_frac_ops

2013-12-19 11:45:17 -08:00

clk-gpt-synth.c

Viresh has moved

2012-06-20 14:39:36 -07:00

clk-vco-pll.c

clk: SPEAr: Vco-pll: Fix compilation warning

2012-10-29 11:04:34 -07:00

clk.c

CLK: SPEAr: Correct index scanning done for clock synths

2012-11-21 11:46:06 -08:00

clk.h

Viresh has moved

2012-06-20 14:39:36 -07:00

Makefile

SPEAr13xx: Add common clock framework support

2012-05-14 17:34:05 +02:00

spear3xx_clock.c

clk: spear3xx: Set proper clock parent of uart1/2

2014-07-13 07:12:11 -07:00

spear6xx_clock.c

clk: add CLK_SET_RATE_NO_REPARENT flag

2013-08-19 12:27:17 -07:00

spear1310_clock.c

clk: add CLK_SET_RATE_NO_REPARENT flag

2013-08-19 12:27:17 -07:00

spear1340_clock.c

clk: add CLK_SET_RATE_NO_REPARENT flag

2013-08-19 12:27:17 -07:00