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9f94f545f2
The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
rate change requests to its parent, so that DVFS for the GPU can work
properly.
Fixes: acddfc2c26 ("clk: mediatek: Add MT8183 clock support")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2018 MediaTek Inc.
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// Author: Weiyi Lu <weiyi.lu@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8183-clk.h>
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static const struct mtk_gate_regs mfg_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_MFG(_id, _name, _parent, _shift) \
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GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
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static const struct mtk_gate mfg_clks[] = {
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GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
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};
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static const struct mtk_clk_desc mfg_desc = {
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.clks = mfg_clks,
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.num_clks = ARRAY_SIZE(mfg_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_mfg[] = {
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{
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.compatible = "mediatek,mt8183-mfgcfg",
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.data = &mfg_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_mfg_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-mfg",
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.of_match_table = of_match_clk_mt8183_mfg,
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},
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};
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builtin_platform_driver(clk_mt8183_mfg_drv);
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