linux-stable/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
Linus Torvalds 480e035fc4 drm for 6.9:
core:
 - EDID cleanups
 - scheduler error handling fixes
 - managed: add drmm_release_action() with tests
 - add ratelimited drm debug print
 - DPCD PSR early transport macro
 - DP tunneling and bandwidth allocation helpers
 - remove built-in edids
 - dp: Avoid AUX transfers on powered-down displays
 - dp: Add VSC SDP helpers
 
 cross drivers:
 - use new drm print helpers
 - switch to ->read_edid callback
 - gem: add stats for shared buffers plus updates to amdgpu, i915, xe
 
 syncobj:
 - fixes to waiting and sleeping
 
 ttm:
 - add tests
 - fix errno codes
 - simply busy-placement handling
 - fix page decryption
 
 media:
 - tc358743: fix v4l device registration
 
 video:
 - move all kernel parameters for video behind CONFIG_VIDEO
 
 sound:
 - remove <drm/drm_edid.h> include from header
 
 ci:
 - add tests for msm
 - fix apq8016 runner
 
 efifb:
 - use copy of global screen_info state
 
 vesafb:
 - use copy of global screen_info state
 
 simplefb:
 - fix logging
 
 bridge:
 - ite-6505: fix DP link-training bug
 - samsung-dsim: fix error checking in probe
 - samsung-dsim: add bsh-smm-s2/pro boards
 - tc358767: fix regmap usage
 - imx: add i.MX8MP HDMI PVI plus DT bindings
 - imx: add i.MX8MP HDMI TX plus DT bindings
 - sii902x: fix probing and unregistration
 - tc358767: limit pixel PLL input range
 - switch to new drm_bridge_read_edid() interface
 
 panel:
 - ltk050h3146w: error-handling fixes
 - panel-edp: support delay between power-on and enable; use put_sync in
   unprepare; support Mediatek MT8173 Chromebooks, BOE NV116WHM-N49 V8.0,
   BOE NV122WUM-N41, CSO MNC207QS1-1 plus DT bindings
 - panel-lvds: support EDT ETML0700Z9NDHA plus DT bindings
 - panel-novatek: FRIDA FRD400B25025-A-CTK plus DT bindings
 - add BOE TH101MB31IG002-28A plus DT bindings
 - add EDT ETML1010G3DRA plus DT bindings
 - add Novatek NT36672E LCD DSI plus DT bindings
 - nt36523: support 120Hz timings, fix includes
 - simple: fix display timings on RK32FN48H
 - visionox-vtdr6130: fix initialization
 - add Powkiddy RGB10MAX3 plus DT bindings
 - st7703: support panel rotation plus DT bindings
 - add Himax HX83112A plus DT bindings
 - ltk500hd1829: add support for ltk101b4029w and admatec 9904370
 - simple: add BOE BP082WX1-100 8.2" panel plus DT bindungs
 
 panel-orientation-quirks:
 - GPD Win Mini
 
 amdgpu:
 - Validate DMABuf imports in compute VMs
 - Add RAS ACA framework
 - PSP 13 fixes
 - Misc code cleanups
 - Replay fixes
 - Atom interpretor PS, WS bounds checking
 - DML2 fixes
 - Audio fixes
 - DCN 3.5 Z state fixes
 - Remove deprecated ida_simple usage
 - UBSAN fixes
 - RAS fixes
 - Enable seq64 infrastructure
 - DC color block enablement
 - Documentation updates
 - DC documentation updates
 - DMCUB updates
 - ATHUB 4.1 support
 - LSDMA 7.0 support
 - JPEG DPG support
 - IH 7.0 support
 - HDP 7.0 support
 - VCN 5.0 support
 - SMU 13.0.6 updates
 - NBIO 7.11 updates
 - SDMA 6.1 updates
 - MMHUB 3.3 updates
 - DCN 3.5.1 support
 - NBIF 6.3.1 support
 - VPE 6.1.1 support
 
 amdkfd:
 - Validate DMABuf imports in compute VMs
 - SVM fixes
 - Trap handler updates and enhancements
 - Fix cache size reporting
 - Relocate the trap handler
 
 radeon:
 - Atom interpretor PS, WS bounds checking
 - Misc code cleanups
 
 xe:
 - new query for GuC submission version
 - Remove unused persistent exec_queues
 - Add vram frequency sysfs attributes
 - Add the flag XE_VM_BIND_FLAG_DUMPABLE
 - Drop pre-production workarounds
 - Drop kunit tests for unsupported platforms
 - Start pumbling SR-IOV support with memory based interrupts for VF
 - Allow to map BO in GGTT with PAT index corresponding to
   XE_CACHE_UC to work with memory based interrupts
 - Add GuC Doorbells Manager as prep work SR-IOV
 - Implement additional workarounds for xe2 and MTL
 - Program a few registers according to perfomance guide spec for Xe2
 - Fix remaining 32b build issues and enable it back
 - Fix build with CONFIG_DEBUG_FS=n
 - Fix warnings from GuC ABI headers
 - Introduce Relay Communication for SR-IOV for VF <-> GuC <-> PF
 - Release mmap mappings on rpm suspend
 - Disable mid-thread preemption when not properly supported by hardware
 - Fix xe_exec by reserving extra fence slot for CPU bind
 - Fix xe_exec with full long running exec queue
 - Canonicalize addresses where needed for Xe2 and add to devcoredum
 - Toggle USM support for Xe2
 - Only allow 1 ufence per exec / bind IOCTL
 - Add GuC firmware loading for Lunar Lake
 - Add XE_VMA_PTE_64K VMA flag
 
 i915:
 - Add more ADL-N PCI IDs
 - Enable fastboot also on older platforms
 - Early transport for panel replay and PSR
 - New ARL PCI IDs
 - DP TPS4 PHY test pattern support
 - Unify and improve VSC SDP for PSR and non-PSR cases
 - Refactor memory regions and improve debug logging
 - Rework global state serialization
 - Remove unused CDCLK divider fields
 - Unify HDCP connector logging format
 - Use display instead of graphics version in display code
 - Move VBT and opregion debugfs next to the implementation
 - Abstract opregion interface, use opaque type
 - MTL fixes
 - HPD handling fixes
 - Add GuC submission interface version query
 - Atomically invalidate userptr on mmu-notifier
 - Update handling of MMIO triggered reports
 - Don't make assumptions about intel_wakeref_t type
 - Extend driver code of Xe_LPG to Xe_LPG+
 - Add flex arrays to struct i915_syncmap
 - Allow for very slow HuC loading
 - DP tunneling and bandwidth allocation support
 
 msm:
 - Correct bindings for MSM8976 and SM8650 platforms
 - Start migration of MDP5 platforms to DPU driver
 - X1E80100 MDSS support
 - DPU:
 - Improve DSC allocation, fixing several important corner cases
 - Add support for SDM630/SDM660 platforms
 - Simplify dpu_encoder_phys_ops
 - Apply fixes targeting DSC support with a single DSC encoder
 - Apply fixes for HCTL_EN timing configuration
 - X1E80100 support
 - Add support for YUV420 over DP
 - GPU:
 - fix sc7180 UBWC config
 - fix a7xx LLC config
 - new gpu support: a305B, a750, a702
 - machine support: SM7150 (different power levels than other a618)
 - a7xx devcoredump support
 
 habanalabs:
 - configure IRQ affinity according to NUMA node
 - move HBM MMU page tables inside the HBM
 - improve device reset
 - check extended PCIe errors
 
 ivpu:
 - updates to firmware API
 - refactor BO allocation
 
 imx:
 - use devm_ functions during init
 
 hisilicon:
 - fix EDID includes
 
 mgag200:
 - improve ioremap usage
 - convert to struct drm_edid
 - Work around PCI write bursts
 
 nouveau:
 - disp: use kmemdup()
 - fix EDID includes
 - documentation fixes
 
 qaic:
 - fixes to BO handling
 - make use of DRM managed release
 - fix order of remove operations
 
 rockchip:
 - analogix_dp: get encoder port from DT
 - inno_hdmi: support HDMI for RK3128
 - lvds: error-handling fixes
 
 ssd130x:
 - support SSD133x plus DT bindings
 
 tegra:
 - fix error handling
 
 tilcdc:
 - make use of DRM managed release
 
 v3d:
 - show memory stats in debugfs
 - Support display MMU page size
 
 vc4:
 - fix error handling in plane prepare_fb
 - fix framebuffer test in plane helpers
 
 virtio:
 - add venus capset defines
 
 vkms:
 - fix OOB access when programming the LUT
 - Kconfig improvements
 
 vmwgfx:
 - unmap surface before changing plane state
 - fix memory leak in error handling
 - documentation fixes
 - list command SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 as invalid
 - fix null-pointer deref in execbuf
 - refactor display-mode probing
 - fix fencing for creating cursor MOBs
 - fix cursor-memory lifetime
 
 xlnx:
 - fix live video input for ZynqMP DPSUB
 
 lima:
 - fix memory leak
 
 loongson:
 - fail if no VRAM present
 
 meson:
 - switch to new drm_bridge_read_edid() interface
 
 renesas:
 - add RZ/G2L DU support plus DT bindings
 
 mxsfb:
 - Use managed mode config
 
 sun4i:
 - HDMI: updates to atomic mode setting
 
 mediatek:
 - Add display driver for MT8188 VDOSYS1
 - DSI driver cleanups
 - Filter modes according to hardware capability
 - Fix a null pointer crash in mtk_drm_crtc_finish_page_flip
 
 etnaviv:
 - enhancements for NPU and MRT support
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Merge tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "Highlights are usual, more AMD IP blocks for future hw, i915/xe
  changes, Displayport tunnelling support for i915, msm YUV over DP
  changes, new tests for ttm, but its mostly a lot of stuff all over the
  place from lots of people.

  core:
   - EDID cleanups
   - scheduler error handling fixes
   - managed: add drmm_release_action() with tests
   - add ratelimited drm debug print
   - DPCD PSR early transport macro
   - DP tunneling and bandwidth allocation helpers
   - remove built-in edids
   - dp: Avoid AUX transfers on powered-down displays
   - dp: Add VSC SDP helpers

  cross drivers:
   - use new drm print helpers
   - switch to ->read_edid callback
   - gem: add stats for shared buffers plus updates to amdgpu, i915, xe

  syncobj:
   - fixes to waiting and sleeping

  ttm:
   - add tests
   - fix errno codes
   - simply busy-placement handling
   - fix page decryption

  media:
   - tc358743: fix v4l device registration

  video:
   - move all kernel parameters for video behind CONFIG_VIDEO

  sound:
   - remove <drm/drm_edid.h> include from header

  ci:
   - add tests for msm
   - fix apq8016 runner

  efifb:
   - use copy of global screen_info state

  vesafb:
   - use copy of global screen_info state

  simplefb:
   - fix logging

  bridge:
   - ite-6505: fix DP link-training bug
   - samsung-dsim: fix error checking in probe
   - samsung-dsim: add bsh-smm-s2/pro boards
   - tc358767: fix regmap usage
   - imx: add i.MX8MP HDMI PVI plus DT bindings
   - imx: add i.MX8MP HDMI TX plus DT bindings
   - sii902x: fix probing and unregistration
   - tc358767: limit pixel PLL input range
   - switch to new drm_bridge_read_edid() interface

  panel:
   - ltk050h3146w: error-handling fixes
   - panel-edp: support delay between power-on and enable; use put_sync
     in unprepare; support Mediatek MT8173 Chromebooks, BOE NV116WHM-N49
     V8.0, BOE NV122WUM-N41, CSO MNC207QS1-1 plus DT bindings
   - panel-lvds: support EDT ETML0700Z9NDHA plus DT bindings
   - panel-novatek: FRIDA FRD400B25025-A-CTK plus DT bindings
   - add BOE TH101MB31IG002-28A plus DT bindings
   - add EDT ETML1010G3DRA plus DT bindings
   - add Novatek NT36672E LCD DSI plus DT bindings
   - nt36523: support 120Hz timings, fix includes
   - simple: fix display timings on RK32FN48H
   - visionox-vtdr6130: fix initialization
   - add Powkiddy RGB10MAX3 plus DT bindings
   - st7703: support panel rotation plus DT bindings
   - add Himax HX83112A plus DT bindings
   - ltk500hd1829: add support for ltk101b4029w and admatec 9904370
   - simple: add BOE BP082WX1-100 8.2" panel plus DT bindungs

  panel-orientation-quirks:
   - GPD Win Mini

  amdgpu:
   - Validate DMABuf imports in compute VMs
   - Add RAS ACA framework
   - PSP 13 fixes
   - Misc code cleanups
   - Replay fixes
   - Atom interpretor PS, WS bounds checking
   - DML2 fixes
   - Audio fixes
   - DCN 3.5 Z state fixes
   - Remove deprecated ida_simple usage
   - UBSAN fixes
   - RAS fixes
   - Enable seq64 infrastructure
   - DC color block enablement
   - Documentation updates
   - DC documentation updates
   - DMCUB updates
   - ATHUB 4.1 support
   - LSDMA 7.0 support
   - JPEG DPG support
   - IH 7.0 support
   - HDP 7.0 support
   - VCN 5.0 support
   - SMU 13.0.6 updates
   - NBIO 7.11 updates
   - SDMA 6.1 updates
   - MMHUB 3.3 updates
   - DCN 3.5.1 support
   - NBIF 6.3.1 support
   - VPE 6.1.1 support

  amdkfd:
   - Validate DMABuf imports in compute VMs
   - SVM fixes
   - Trap handler updates and enhancements
   - Fix cache size reporting
   - Relocate the trap handler

  radeon:
   - Atom interpretor PS, WS bounds checking
   - Misc code cleanups

  xe:
   - new query for GuC submission version
   - Remove unused persistent exec_queues
   - Add vram frequency sysfs attributes
   - Add the flag XE_VM_BIND_FLAG_DUMPABLE
   - Drop pre-production workarounds
   - Drop kunit tests for unsupported platforms
   - Start pumbling SR-IOV support with memory based interrupts for VF
   - Allow to map BO in GGTT with PAT index corresponding to XE_CACHE_UC
     to work with memory based interrupts
   - Add GuC Doorbells Manager as prep work SR-IOV
   - Implement additional workarounds for xe2 and MTL
   - Program a few registers according to perfomance guide spec for Xe2
   - Fix remaining 32b build issues and enable it back
   - Fix build with CONFIG_DEBUG_FS=n
   - Fix warnings from GuC ABI headers
   - Introduce Relay Communication for SR-IOV for VF <-> GuC <-> PF
   - Release mmap mappings on rpm suspend
   - Disable mid-thread preemption when not properly supported by
     hardware
   - Fix xe_exec by reserving extra fence slot for CPU bind
   - Fix xe_exec with full long running exec queue
   - Canonicalize addresses where needed for Xe2 and add to devcoredum
   - Toggle USM support for Xe2
   - Only allow 1 ufence per exec / bind IOCTL
   - Add GuC firmware loading for Lunar Lake
   - Add XE_VMA_PTE_64K VMA flag

  i915:
   - Add more ADL-N PCI IDs
   - Enable fastboot also on older platforms
   - Early transport for panel replay and PSR
   - New ARL PCI IDs
   - DP TPS4 PHY test pattern support
   - Unify and improve VSC SDP for PSR and non-PSR cases
   - Refactor memory regions and improve debug logging
   - Rework global state serialization
   - Remove unused CDCLK divider fields
   - Unify HDCP connector logging format
   - Use display instead of graphics version in display code
   - Move VBT and opregion debugfs next to the implementation
   - Abstract opregion interface, use opaque type
   - MTL fixes
   - HPD handling fixes
   - Add GuC submission interface version query
   - Atomically invalidate userptr on mmu-notifier
   - Update handling of MMIO triggered reports
   - Don't make assumptions about intel_wakeref_t type
   - Extend driver code of Xe_LPG to Xe_LPG+
   - Add flex arrays to struct i915_syncmap
   - Allow for very slow HuC loading
   - DP tunneling and bandwidth allocation support

  msm:
   - Correct bindings for MSM8976 and SM8650 platforms
   - Start migration of MDP5 platforms to DPU driver
   - X1E80100 MDSS support
   - DPU:
      - Improve DSC allocation, fixing several important corner cases
      - Add support for SDM630/SDM660 platforms
      - Simplify dpu_encoder_phys_ops
      - Apply fixes targeting DSC support with a single DSC encoder
      - Apply fixes for HCTL_EN timing configuration
      - X1E80100 support
      - Add support for YUV420 over DP
   - GPU:
      - fix sc7180 UBWC config
      - fix a7xx LLC config
      - new gpu support: a305B, a750, a702
      - machine support: SM7150 (different power levels than other a618)
      - a7xx devcoredump support

  habanalabs:
   - configure IRQ affinity according to NUMA node
   - move HBM MMU page tables inside the HBM
   - improve device reset
   - check extended PCIe errors

  ivpu:
   - updates to firmware API
   - refactor BO allocation

  imx:
   - use devm_ functions during init

  hisilicon:
   - fix EDID includes

  mgag200:
   - improve ioremap usage
   - convert to struct drm_edid
   - Work around PCI write bursts

  nouveau:
   - disp: use kmemdup()
   - fix EDID includes
   - documentation fixes

  qaic:
   - fixes to BO handling
   - make use of DRM managed release
   - fix order of remove operations

  rockchip:
   - analogix_dp: get encoder port from DT
   - inno_hdmi: support HDMI for RK3128
   - lvds: error-handling fixes

  ssd130x:
   - support SSD133x plus DT bindings

  tegra:
   - fix error handling

  tilcdc:
   - make use of DRM managed release

  v3d:
   - show memory stats in debugfs
   - Support display MMU page size

  vc4:
   - fix error handling in plane prepare_fb
   - fix framebuffer test in plane helpers

  virtio:
   - add venus capset defines

  vkms:
   - fix OOB access when programming the LUT
   - Kconfig improvements

  vmwgfx:
   - unmap surface before changing plane state
   - fix memory leak in error handling
   - documentation fixes
   - list command SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 as invalid
   - fix null-pointer deref in execbuf
   - refactor display-mode probing
   - fix fencing for creating cursor MOBs
   - fix cursor-memory lifetime

  xlnx:
   - fix live video input for ZynqMP DPSUB

  lima:
   - fix memory leak

  loongson:
   - fail if no VRAM present

  meson:
   - switch to new drm_bridge_read_edid() interface

  renesas:
   - add RZ/G2L DU support plus DT bindings

  mxsfb:
   - Use managed mode config

  sun4i:
   - HDMI: updates to atomic mode setting

  mediatek:
   - Add display driver for MT8188 VDOSYS1
   - DSI driver cleanups
   - Filter modes according to hardware capability
   - Fix a null pointer crash in mtk_drm_crtc_finish_page_flip

  etnaviv:
   - enhancements for NPU and MRT support"

* tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel: (1420 commits)
  drm/amd/display: Removed redundant @ symbol to fix kernel-doc warnings in -next repo
  drm/amd/pm: wait for completion of the EnableGfxImu message
  drm/amdgpu/soc21: add mode2 asic reset for SMU IP v14.0.1
  drm/amdgpu: add smu 14.0.1 support
  drm/amdgpu: add VPE 6.1.1 discovery support
  drm/amdgpu/vpe: add VPE 6.1.1 support
  drm/amdgpu/vpe: don't emit cond exec command under collaborate mode
  drm/amdgpu/vpe: add collaborate mode support for VPE
  drm/amdgpu/vpe: add PRED_EXE and COLLAB_SYNC OPCODE
  drm/amdgpu/vpe: add multi instance VPE support
  drm/amdgpu/discovery: add nbif v6_3_1 ip block
  drm/amdgpu: Add nbif v6_3_1 ip block support
  drm/amdgpu: Add pcie v6_1_0 ip headers (v5)
  drm/amdgpu: Add nbif v6_3_1 ip headers (v5)
  arch/powerpc: Remove <linux/fb.h> from backlight code
  macintosh/via-pmu-backlight: Include <linux/backlight.h>
  fbdev/chipsfb: Include <linux/backlight.h>
  drm/etnaviv: Restore some id values
  drm/amdkfd: make kfd_class constant
  drm/amdgpu: add ring timeout information in devcoredump
  ...
2024-03-13 18:34:05 -07:00

1994 lines
55 KiB
C

// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Jitao Shi <jitao.shi@mediatek.com>
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <drm/drm_connector.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include <video/mipi_display.h>
struct panel_desc {
const struct drm_display_mode *modes;
unsigned int bpc;
/**
* @width_mm: width of the panel's active display area
* @height_mm: height of the panel's active display area
*/
struct {
unsigned int width_mm;
unsigned int height_mm;
} size;
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
const struct panel_init_cmd *init_cmds;
unsigned int lanes;
bool discharge_on_disable;
bool lp11_before_reset;
};
struct boe_panel {
struct drm_panel base;
struct mipi_dsi_device *dsi;
const struct panel_desc *desc;
enum drm_panel_orientation orientation;
struct regulator *pp3300;
struct regulator *pp1800;
struct regulator *avee;
struct regulator *avdd;
struct gpio_desc *enable_gpio;
bool prepared;
};
enum dsi_cmd_type {
INIT_DCS_CMD,
DELAY_CMD,
};
struct panel_init_cmd {
enum dsi_cmd_type type;
size_t len;
const char *data;
};
#define _INIT_DCS_CMD(...) { \
.type = INIT_DCS_CMD, \
.len = sizeof((char[]){__VA_ARGS__}), \
.data = (char[]){__VA_ARGS__} }
#define _INIT_DELAY_CMD(...) { \
.type = DELAY_CMD,\
.len = sizeof((char[]){__VA_ARGS__}), \
.data = (char[]){__VA_ARGS__} }
static const struct panel_init_cmd boe_tv110c9m_init_cmd[] = {
_INIT_DCS_CMD(0xFF, 0x20),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x05, 0xD9),
_INIT_DCS_CMD(0x07, 0x78),
_INIT_DCS_CMD(0x08, 0x5A),
_INIT_DCS_CMD(0x0D, 0x63),
_INIT_DCS_CMD(0x0E, 0x91),
_INIT_DCS_CMD(0x0F, 0x73),
_INIT_DCS_CMD(0x95, 0xE6),
_INIT_DCS_CMD(0x96, 0xF0),
_INIT_DCS_CMD(0x30, 0x00),
_INIT_DCS_CMD(0x6D, 0x66),
_INIT_DCS_CMD(0x75, 0xA2),
_INIT_DCS_CMD(0x77, 0x3B),
_INIT_DCS_CMD(0xB0, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00, 0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9),
_INIT_DCS_CMD(0xB1, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01, 0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31),
_INIT_DCS_CMD(0xB2, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03, 0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B),
_INIT_DCS_CMD(0xB3, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03, 0xFD, 0x03, 0xFF),
_INIT_DCS_CMD(0xB4, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00, 0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9),
_INIT_DCS_CMD(0xB5, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01, 0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31),
_INIT_DCS_CMD(0xB6, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03, 0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B),
_INIT_DCS_CMD(0xB7, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03, 0xFD, 0x03, 0xFF),
_INIT_DCS_CMD(0xB8, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00, 0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9),
_INIT_DCS_CMD(0xB9, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01, 0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31),
_INIT_DCS_CMD(0xBA, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03, 0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B),
_INIT_DCS_CMD(0xBB, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03, 0xFD, 0x03, 0xFF),
_INIT_DCS_CMD(0xFF, 0x21),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1),
_INIT_DCS_CMD(0xB1, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01, 0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29),
_INIT_DCS_CMD(0xB2, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73),
_INIT_DCS_CMD(0xB3, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03, 0xF5, 0x03, 0xE0),
_INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1),
_INIT_DCS_CMD(0xB5, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01, 0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29),
_INIT_DCS_CMD(0xB6, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73),
_INIT_DCS_CMD(0xB7, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03, 0xF5, 0x03, 0xE0),
_INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1),
_INIT_DCS_CMD(0xB9, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01, 0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29),
_INIT_DCS_CMD(0xBA, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73),
_INIT_DCS_CMD(0xBB, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03, 0xF5, 0x03, 0xE0),
_INIT_DCS_CMD(0xFF, 0x24),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x00, 0x00),
_INIT_DCS_CMD(0x01, 0x00),
_INIT_DCS_CMD(0x02, 0x1C),
_INIT_DCS_CMD(0x03, 0x1C),
_INIT_DCS_CMD(0x04, 0x1D),
_INIT_DCS_CMD(0x05, 0x1D),
_INIT_DCS_CMD(0x06, 0x04),
_INIT_DCS_CMD(0x07, 0x04),
_INIT_DCS_CMD(0x08, 0x0F),
_INIT_DCS_CMD(0x09, 0x0F),
_INIT_DCS_CMD(0x0A, 0x0E),
_INIT_DCS_CMD(0x0B, 0x0E),
_INIT_DCS_CMD(0x0C, 0x0D),
_INIT_DCS_CMD(0x0D, 0x0D),
_INIT_DCS_CMD(0x0E, 0x0C),
_INIT_DCS_CMD(0x0F, 0x0C),
_INIT_DCS_CMD(0x10, 0x08),
_INIT_DCS_CMD(0x11, 0x08),
_INIT_DCS_CMD(0x12, 0x00),
_INIT_DCS_CMD(0x13, 0x00),
_INIT_DCS_CMD(0x14, 0x00),
_INIT_DCS_CMD(0x15, 0x00),
_INIT_DCS_CMD(0x16, 0x00),
_INIT_DCS_CMD(0x17, 0x00),
_INIT_DCS_CMD(0x18, 0x1C),
_INIT_DCS_CMD(0x19, 0x1C),
_INIT_DCS_CMD(0x1A, 0x1D),
_INIT_DCS_CMD(0x1B, 0x1D),
_INIT_DCS_CMD(0x1C, 0x04),
_INIT_DCS_CMD(0x1D, 0x04),
_INIT_DCS_CMD(0x1E, 0x0F),
_INIT_DCS_CMD(0x1F, 0x0F),
_INIT_DCS_CMD(0x20, 0x0E),
_INIT_DCS_CMD(0x21, 0x0E),
_INIT_DCS_CMD(0x22, 0x0D),
_INIT_DCS_CMD(0x23, 0x0D),
_INIT_DCS_CMD(0x24, 0x0C),
_INIT_DCS_CMD(0x25, 0x0C),
_INIT_DCS_CMD(0x26, 0x08),
_INIT_DCS_CMD(0x27, 0x08),
_INIT_DCS_CMD(0x28, 0x00),
_INIT_DCS_CMD(0x29, 0x00),
_INIT_DCS_CMD(0x2A, 0x00),
_INIT_DCS_CMD(0x2B, 0x00),
_INIT_DCS_CMD(0x2D, 0x20),
_INIT_DCS_CMD(0x2F, 0x0A),
_INIT_DCS_CMD(0x30, 0x44),
_INIT_DCS_CMD(0x33, 0x0C),
_INIT_DCS_CMD(0x34, 0x32),
_INIT_DCS_CMD(0x37, 0x44),
_INIT_DCS_CMD(0x38, 0x40),
_INIT_DCS_CMD(0x39, 0x00),
_INIT_DCS_CMD(0x3A, 0x5D),
_INIT_DCS_CMD(0x3B, 0x60),
_INIT_DCS_CMD(0x3D, 0x42),
_INIT_DCS_CMD(0x3F, 0x06),
_INIT_DCS_CMD(0x43, 0x06),
_INIT_DCS_CMD(0x47, 0x66),
_INIT_DCS_CMD(0x4A, 0x5D),
_INIT_DCS_CMD(0x4B, 0x60),
_INIT_DCS_CMD(0x4C, 0x91),
_INIT_DCS_CMD(0x4D, 0x21),
_INIT_DCS_CMD(0x4E, 0x43),
_INIT_DCS_CMD(0x51, 0x12),
_INIT_DCS_CMD(0x52, 0x34),
_INIT_DCS_CMD(0x55, 0x82, 0x02),
_INIT_DCS_CMD(0x56, 0x04),
_INIT_DCS_CMD(0x58, 0x21),
_INIT_DCS_CMD(0x59, 0x30),
_INIT_DCS_CMD(0x5A, 0x60),
_INIT_DCS_CMD(0x5B, 0x50),
_INIT_DCS_CMD(0x5E, 0x00, 0x06),
_INIT_DCS_CMD(0x5F, 0x00),
_INIT_DCS_CMD(0x65, 0x82),
_INIT_DCS_CMD(0x7E, 0x20),
_INIT_DCS_CMD(0x7F, 0x3C),
_INIT_DCS_CMD(0x82, 0x04),
_INIT_DCS_CMD(0x97, 0xC0),
_INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00),
_INIT_DCS_CMD(0x91, 0x44),
_INIT_DCS_CMD(0x92, 0xA9),
_INIT_DCS_CMD(0x93, 0x1A),
_INIT_DCS_CMD(0x94, 0x96),
_INIT_DCS_CMD(0xD7, 0x55),
_INIT_DCS_CMD(0xDA, 0x0A),
_INIT_DCS_CMD(0xDE, 0x08),
_INIT_DCS_CMD(0xDB, 0x05),
_INIT_DCS_CMD(0xDC, 0xA9),
_INIT_DCS_CMD(0xDD, 0x22),
_INIT_DCS_CMD(0xDF, 0x05),
_INIT_DCS_CMD(0xE0, 0xA9),
_INIT_DCS_CMD(0xE1, 0x05),
_INIT_DCS_CMD(0xE2, 0xA9),
_INIT_DCS_CMD(0xE3, 0x05),
_INIT_DCS_CMD(0xE4, 0xA9),
_INIT_DCS_CMD(0xE5, 0x05),
_INIT_DCS_CMD(0xE6, 0xA9),
_INIT_DCS_CMD(0x5C, 0x00),
_INIT_DCS_CMD(0x5D, 0x00),
_INIT_DCS_CMD(0x8D, 0x00),
_INIT_DCS_CMD(0x8E, 0x00),
_INIT_DCS_CMD(0xB5, 0x90),
_INIT_DCS_CMD(0xFF, 0x25),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x05, 0x00),
_INIT_DCS_CMD(0x19, 0x07),
_INIT_DCS_CMD(0x1F, 0x60),
_INIT_DCS_CMD(0x20, 0x50),
_INIT_DCS_CMD(0x26, 0x60),
_INIT_DCS_CMD(0x27, 0x50),
_INIT_DCS_CMD(0x33, 0x60),
_INIT_DCS_CMD(0x34, 0x50),
_INIT_DCS_CMD(0x3F, 0xE0),
_INIT_DCS_CMD(0x40, 0x00),
_INIT_DCS_CMD(0x44, 0x00),
_INIT_DCS_CMD(0x45, 0x40),
_INIT_DCS_CMD(0x48, 0x60),
_INIT_DCS_CMD(0x49, 0x50),
_INIT_DCS_CMD(0x5B, 0x00),
_INIT_DCS_CMD(0x5C, 0x00),
_INIT_DCS_CMD(0x5D, 0x00),
_INIT_DCS_CMD(0x5E, 0xD0),
_INIT_DCS_CMD(0x61, 0x60),
_INIT_DCS_CMD(0x62, 0x50),
_INIT_DCS_CMD(0xF1, 0x10),
_INIT_DCS_CMD(0xFF, 0x2A),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x64, 0x16),
_INIT_DCS_CMD(0x67, 0x16),
_INIT_DCS_CMD(0x6A, 0x16),
_INIT_DCS_CMD(0x70, 0x30),
_INIT_DCS_CMD(0xA2, 0xF3),
_INIT_DCS_CMD(0xA3, 0xFF),
_INIT_DCS_CMD(0xA4, 0xFF),
_INIT_DCS_CMD(0xA5, 0xFF),
_INIT_DCS_CMD(0xD6, 0x08),
_INIT_DCS_CMD(0xFF, 0x26),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x00, 0xA1),
_INIT_DCS_CMD(0x02, 0x31),
_INIT_DCS_CMD(0x04, 0x28),
_INIT_DCS_CMD(0x06, 0x30),
_INIT_DCS_CMD(0x0C, 0x16),
_INIT_DCS_CMD(0x0D, 0x0D),
_INIT_DCS_CMD(0x0F, 0x00),
_INIT_DCS_CMD(0x11, 0x00),
_INIT_DCS_CMD(0x12, 0x50),
_INIT_DCS_CMD(0x13, 0x56),
_INIT_DCS_CMD(0x14, 0x57),
_INIT_DCS_CMD(0x15, 0x00),
_INIT_DCS_CMD(0x16, 0x10),
_INIT_DCS_CMD(0x17, 0xA0),
_INIT_DCS_CMD(0x18, 0x86),
_INIT_DCS_CMD(0x19, 0x0D),
_INIT_DCS_CMD(0x1A, 0x7F),
_INIT_DCS_CMD(0x1B, 0x0C),
_INIT_DCS_CMD(0x1C, 0xBF),
_INIT_DCS_CMD(0x22, 0x00),
_INIT_DCS_CMD(0x23, 0x00),
_INIT_DCS_CMD(0x2A, 0x0D),
_INIT_DCS_CMD(0x2B, 0x7F),
_INIT_DCS_CMD(0x1D, 0x00),
_INIT_DCS_CMD(0x1E, 0x65),
_INIT_DCS_CMD(0x1F, 0x65),
_INIT_DCS_CMD(0x24, 0x00),
_INIT_DCS_CMD(0x25, 0x65),
_INIT_DCS_CMD(0x2F, 0x05),
_INIT_DCS_CMD(0x30, 0x65),
_INIT_DCS_CMD(0x31, 0x05),
_INIT_DCS_CMD(0x32, 0x7D),
_INIT_DCS_CMD(0x39, 0x00),
_INIT_DCS_CMD(0x3A, 0x65),
_INIT_DCS_CMD(0x20, 0x01),
_INIT_DCS_CMD(0x33, 0x11),
_INIT_DCS_CMD(0x34, 0x78),
_INIT_DCS_CMD(0x35, 0x16),
_INIT_DCS_CMD(0xC8, 0x04),
_INIT_DCS_CMD(0xC9, 0x9E),
_INIT_DCS_CMD(0xCA, 0x4E),
_INIT_DCS_CMD(0xCB, 0x00),
_INIT_DCS_CMD(0xA9, 0x49),
_INIT_DCS_CMD(0xAA, 0x4B),
_INIT_DCS_CMD(0xAB, 0x48),
_INIT_DCS_CMD(0xAC, 0x43),
_INIT_DCS_CMD(0xAD, 0x40),
_INIT_DCS_CMD(0xAE, 0x50),
_INIT_DCS_CMD(0xAF, 0x44),
_INIT_DCS_CMD(0xB0, 0x54),
_INIT_DCS_CMD(0xB1, 0x4E),
_INIT_DCS_CMD(0xB2, 0x4D),
_INIT_DCS_CMD(0xB3, 0x4C),
_INIT_DCS_CMD(0xB4, 0x41),
_INIT_DCS_CMD(0xB5, 0x47),
_INIT_DCS_CMD(0xB6, 0x53),
_INIT_DCS_CMD(0xB7, 0x3E),
_INIT_DCS_CMD(0xB8, 0x51),
_INIT_DCS_CMD(0xB9, 0x3C),
_INIT_DCS_CMD(0xBA, 0x3B),
_INIT_DCS_CMD(0xBB, 0x46),
_INIT_DCS_CMD(0xBC, 0x45),
_INIT_DCS_CMD(0xBD, 0x55),
_INIT_DCS_CMD(0xBE, 0x3D),
_INIT_DCS_CMD(0xBF, 0x3F),
_INIT_DCS_CMD(0xC0, 0x52),
_INIT_DCS_CMD(0xC1, 0x4A),
_INIT_DCS_CMD(0xC2, 0x39),
_INIT_DCS_CMD(0xC3, 0x4F),
_INIT_DCS_CMD(0xC4, 0x3A),
_INIT_DCS_CMD(0xC5, 0x42),
_INIT_DCS_CMD(0xFF, 0x27),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x56, 0x06),
_INIT_DCS_CMD(0x58, 0x80),
_INIT_DCS_CMD(0x59, 0x75),
_INIT_DCS_CMD(0x5A, 0x00),
_INIT_DCS_CMD(0x5B, 0x02),
_INIT_DCS_CMD(0x5C, 0x00),
_INIT_DCS_CMD(0x5D, 0x00),
_INIT_DCS_CMD(0x5E, 0x20),
_INIT_DCS_CMD(0x5F, 0x10),
_INIT_DCS_CMD(0x60, 0x00),
_INIT_DCS_CMD(0x61, 0x2E),
_INIT_DCS_CMD(0x62, 0x00),
_INIT_DCS_CMD(0x63, 0x01),
_INIT_DCS_CMD(0x64, 0x43),
_INIT_DCS_CMD(0x65, 0x2D),
_INIT_DCS_CMD(0x66, 0x00),
_INIT_DCS_CMD(0x67, 0x01),
_INIT_DCS_CMD(0x68, 0x44),
_INIT_DCS_CMD(0x00, 0x00),
_INIT_DCS_CMD(0x78, 0x00),
_INIT_DCS_CMD(0xC3, 0x00),
_INIT_DCS_CMD(0xFF, 0x2A),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x22, 0x2F),
_INIT_DCS_CMD(0x23, 0x08),
_INIT_DCS_CMD(0x24, 0x00),
_INIT_DCS_CMD(0x25, 0x65),
_INIT_DCS_CMD(0x26, 0xF8),
_INIT_DCS_CMD(0x27, 0x00),
_INIT_DCS_CMD(0x28, 0x1A),
_INIT_DCS_CMD(0x29, 0x00),
_INIT_DCS_CMD(0x2A, 0x1A),
_INIT_DCS_CMD(0x2B, 0x00),
_INIT_DCS_CMD(0x2D, 0x1A),
_INIT_DCS_CMD(0xFF, 0x23),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x00, 0x80),
_INIT_DCS_CMD(0x07, 0x00),
_INIT_DCS_CMD(0xFF, 0xE0),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x14, 0x60),
_INIT_DCS_CMD(0x16, 0xC0),
_INIT_DCS_CMD(0xFF, 0xF0),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x3A, 0x08),
_INIT_DCS_CMD(0xFF, 0x10),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0xB9, 0x01),
_INIT_DCS_CMD(0xFF, 0x20),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x18, 0x40),
_INIT_DCS_CMD(0xFF, 0x10),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0xB9, 0x02),
_INIT_DCS_CMD(0x35, 0x00),
_INIT_DCS_CMD(0x51, 0x00, 0xFF),
_INIT_DCS_CMD(0x53, 0x24),
_INIT_DCS_CMD(0x55, 0x00),
_INIT_DCS_CMD(0xBB, 0x13),
_INIT_DCS_CMD(0x3B, 0x03, 0x96, 0x1A, 0x04, 0x04),
_INIT_DELAY_CMD(100),
_INIT_DCS_CMD(0x11),
_INIT_DELAY_CMD(200),
_INIT_DCS_CMD(0x29),
_INIT_DELAY_CMD(100),
{},
};
static const struct panel_init_cmd inx_hj110iz_init_cmd[] = {
_INIT_DCS_CMD(0xFF, 0x20),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x05, 0xD1),
_INIT_DCS_CMD(0x06, 0xC0),
_INIT_DCS_CMD(0x07, 0x87),
_INIT_DCS_CMD(0x08, 0x4B),
_INIT_DCS_CMD(0x0D, 0x63),
_INIT_DCS_CMD(0x0E, 0x91),
_INIT_DCS_CMD(0x0F, 0x69),
_INIT_DCS_CMD(0x94, 0x00),
_INIT_DCS_CMD(0x95, 0xF5),
_INIT_DCS_CMD(0x96, 0xF5),
_INIT_DCS_CMD(0x9D, 0x00),
_INIT_DCS_CMD(0x9E, 0x00),
_INIT_DCS_CMD(0x69, 0x98),
_INIT_DCS_CMD(0x75, 0xA2),
_INIT_DCS_CMD(0x77, 0xB3),
_INIT_DCS_CMD(0x58, 0x43),
_INIT_DCS_CMD(0xFF, 0x24),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x91, 0x44),
_INIT_DCS_CMD(0x92, 0x4C),
_INIT_DCS_CMD(0x94, 0x86),
_INIT_DCS_CMD(0x60, 0x96),
_INIT_DCS_CMD(0x61, 0xD0),
_INIT_DCS_CMD(0x63, 0x70),
_INIT_DCS_CMD(0xC2, 0xCA),
_INIT_DCS_CMD(0x00, 0x03),
_INIT_DCS_CMD(0x01, 0x03),
_INIT_DCS_CMD(0x02, 0x03),
_INIT_DCS_CMD(0x03, 0x29),
_INIT_DCS_CMD(0x04, 0x22),
_INIT_DCS_CMD(0x05, 0x22),
_INIT_DCS_CMD(0x06, 0x0B),
_INIT_DCS_CMD(0x07, 0x1D),
_INIT_DCS_CMD(0x08, 0x1C),
_INIT_DCS_CMD(0x09, 0x05),
_INIT_DCS_CMD(0x0A, 0x08),
_INIT_DCS_CMD(0x0B, 0x09),
_INIT_DCS_CMD(0x0C, 0x0A),
_INIT_DCS_CMD(0x0D, 0x0C),
_INIT_DCS_CMD(0x0E, 0x0D),
_INIT_DCS_CMD(0x0F, 0x0E),
_INIT_DCS_CMD(0x10, 0x0F),
_INIT_DCS_CMD(0x11, 0x10),
_INIT_DCS_CMD(0x12, 0x11),
_INIT_DCS_CMD(0x13, 0x04),
_INIT_DCS_CMD(0x14, 0x00),
_INIT_DCS_CMD(0x15, 0x03),
_INIT_DCS_CMD(0x16, 0x03),
_INIT_DCS_CMD(0x17, 0x03),
_INIT_DCS_CMD(0x18, 0x03),
_INIT_DCS_CMD(0x19, 0x29),
_INIT_DCS_CMD(0x1A, 0x22),
_INIT_DCS_CMD(0x1B, 0x22),
_INIT_DCS_CMD(0x1C, 0x0B),
_INIT_DCS_CMD(0x1D, 0x1D),
_INIT_DCS_CMD(0x1E, 0x1C),
_INIT_DCS_CMD(0x1F, 0x05),
_INIT_DCS_CMD(0x20, 0x08),
_INIT_DCS_CMD(0x21, 0x09),
_INIT_DCS_CMD(0x22, 0x0A),
_INIT_DCS_CMD(0x23, 0x0C),
_INIT_DCS_CMD(0x24, 0x0D),
_INIT_DCS_CMD(0x25, 0x0E),
_INIT_DCS_CMD(0x26, 0x0F),
_INIT_DCS_CMD(0x27, 0x10),
_INIT_DCS_CMD(0x28, 0x11),
_INIT_DCS_CMD(0x29, 0x04),
_INIT_DCS_CMD(0x2A, 0x00),
_INIT_DCS_CMD(0x2B, 0x03),
_INIT_DCS_CMD(0x2F, 0x0A),
_INIT_DCS_CMD(0x30, 0x35),
_INIT_DCS_CMD(0x37, 0xA7),
_INIT_DCS_CMD(0x39, 0x00),
_INIT_DCS_CMD(0x3A, 0x46),
_INIT_DCS_CMD(0x3B, 0x32),
_INIT_DCS_CMD(0x3D, 0x12),
_INIT_DCS_CMD(0x3F, 0x33),
_INIT_DCS_CMD(0x40, 0x31),
_INIT_DCS_CMD(0x41, 0x40),
_INIT_DCS_CMD(0x42, 0x42),
_INIT_DCS_CMD(0x47, 0x77),
_INIT_DCS_CMD(0x48, 0x77),
_INIT_DCS_CMD(0x4A, 0x45),
_INIT_DCS_CMD(0x4B, 0x45),
_INIT_DCS_CMD(0x4C, 0x14),
_INIT_DCS_CMD(0x4D, 0x21),
_INIT_DCS_CMD(0x4E, 0x43),
_INIT_DCS_CMD(0x4F, 0x65),
_INIT_DCS_CMD(0x55, 0x06),
_INIT_DCS_CMD(0x56, 0x06),
_INIT_DCS_CMD(0x58, 0x21),
_INIT_DCS_CMD(0x59, 0x70),
_INIT_DCS_CMD(0x5A, 0x46),
_INIT_DCS_CMD(0x5B, 0x32),
_INIT_DCS_CMD(0x5C, 0x88),
_INIT_DCS_CMD(0x5E, 0x00, 0x00),
_INIT_DCS_CMD(0x5F, 0x00),
_INIT_DCS_CMD(0x7A, 0xFF),
_INIT_DCS_CMD(0x7B, 0xFF),
_INIT_DCS_CMD(0x7C, 0x00),
_INIT_DCS_CMD(0x7D, 0x00),
_INIT_DCS_CMD(0x7E, 0x20),
_INIT_DCS_CMD(0x7F, 0x3C),
_INIT_DCS_CMD(0x80, 0x00),
_INIT_DCS_CMD(0x81, 0x00),
_INIT_DCS_CMD(0x82, 0x08),
_INIT_DCS_CMD(0x97, 0x02),
_INIT_DCS_CMD(0xC5, 0x10),
_INIT_DCS_CMD(0xD7, 0x55),
_INIT_DCS_CMD(0xD8, 0x55),
_INIT_DCS_CMD(0xD9, 0x23),
_INIT_DCS_CMD(0xDA, 0x05),
_INIT_DCS_CMD(0xDB, 0x01),
_INIT_DCS_CMD(0xDC, 0x65),
_INIT_DCS_CMD(0xDD, 0x55),
_INIT_DCS_CMD(0xDE, 0x27),
_INIT_DCS_CMD(0xDF, 0x01),
_INIT_DCS_CMD(0xE0, 0x65),
_INIT_DCS_CMD(0xE1, 0x01),
_INIT_DCS_CMD(0xE2, 0x65),
_INIT_DCS_CMD(0xE3, 0x01),
_INIT_DCS_CMD(0xE4, 0x65),
_INIT_DCS_CMD(0xE5, 0x01),
_INIT_DCS_CMD(0xE6, 0x65),
_INIT_DCS_CMD(0xE7, 0x00),
_INIT_DCS_CMD(0xE8, 0x00),
_INIT_DCS_CMD(0xE9, 0x01),
_INIT_DCS_CMD(0xEA, 0x65),
_INIT_DCS_CMD(0xEB, 0x01),
_INIT_DCS_CMD(0xEE, 0x65),
_INIT_DCS_CMD(0xEF, 0x01),
_INIT_DCS_CMD(0xF0, 0x65),
_INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00),
_INIT_DCS_CMD(0xFF, 0x25),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x05, 0x00),
_INIT_DCS_CMD(0xF1, 0x10),
_INIT_DCS_CMD(0x1E, 0x00),
_INIT_DCS_CMD(0x1F, 0x46),
_INIT_DCS_CMD(0x20, 0x32),
_INIT_DCS_CMD(0x25, 0x00),
_INIT_DCS_CMD(0x26, 0x46),
_INIT_DCS_CMD(0x27, 0x32),
_INIT_DCS_CMD(0x3F, 0x80),
_INIT_DCS_CMD(0x40, 0x00),
_INIT_DCS_CMD(0x43, 0x00),
_INIT_DCS_CMD(0x44, 0x46),
_INIT_DCS_CMD(0x45, 0x46),
_INIT_DCS_CMD(0x48, 0x46),
_INIT_DCS_CMD(0x49, 0x32),
_INIT_DCS_CMD(0x5B, 0x80),
_INIT_DCS_CMD(0x5C, 0x00),
_INIT_DCS_CMD(0x5D, 0x46),
_INIT_DCS_CMD(0x5E, 0x32),
_INIT_DCS_CMD(0x5F, 0x46),
_INIT_DCS_CMD(0x60, 0x32),
_INIT_DCS_CMD(0x61, 0x46),
_INIT_DCS_CMD(0x62, 0x32),
_INIT_DCS_CMD(0x68, 0x0C),
_INIT_DCS_CMD(0x6C, 0x0D),
_INIT_DCS_CMD(0x6E, 0x0D),
_INIT_DCS_CMD(0x78, 0x00),
_INIT_DCS_CMD(0x79, 0xC5),
_INIT_DCS_CMD(0x7A, 0x0C),
_INIT_DCS_CMD(0x7B, 0xB0),
_INIT_DCS_CMD(0xFF, 0x26),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x00, 0xA1),
_INIT_DCS_CMD(0x02, 0x31),
_INIT_DCS_CMD(0x0A, 0xF4),
_INIT_DCS_CMD(0x04, 0x50),
_INIT_DCS_CMD(0x06, 0x30),
_INIT_DCS_CMD(0x0C, 0x16),
_INIT_DCS_CMD(0x0D, 0x0D),
_INIT_DCS_CMD(0x0F, 0x00),
_INIT_DCS_CMD(0x11, 0x00),
_INIT_DCS_CMD(0x12, 0x50),
_INIT_DCS_CMD(0x13, 0x40),
_INIT_DCS_CMD(0x14, 0x58),
_INIT_DCS_CMD(0x15, 0x00),
_INIT_DCS_CMD(0x16, 0x10),
_INIT_DCS_CMD(0x17, 0xA0),
_INIT_DCS_CMD(0x18, 0x86),
_INIT_DCS_CMD(0x22, 0x00),
_INIT_DCS_CMD(0x23, 0x00),
_INIT_DCS_CMD(0x19, 0x0E),
_INIT_DCS_CMD(0x1A, 0x31),
_INIT_DCS_CMD(0x1B, 0x0D),
_INIT_DCS_CMD(0x1C, 0x29),
_INIT_DCS_CMD(0x2A, 0x0E),
_INIT_DCS_CMD(0x2B, 0x31),
_INIT_DCS_CMD(0x1D, 0x00),
_INIT_DCS_CMD(0x1E, 0x62),
_INIT_DCS_CMD(0x1F, 0x62),
_INIT_DCS_CMD(0x2F, 0x06),
_INIT_DCS_CMD(0x30, 0x62),
_INIT_DCS_CMD(0x31, 0x06),
_INIT_DCS_CMD(0x32, 0x7F),
_INIT_DCS_CMD(0x33, 0x11),
_INIT_DCS_CMD(0x34, 0x89),
_INIT_DCS_CMD(0x35, 0x67),
_INIT_DCS_CMD(0x39, 0x0B),
_INIT_DCS_CMD(0x3A, 0x62),
_INIT_DCS_CMD(0x3B, 0x06),
_INIT_DCS_CMD(0xC8, 0x04),
_INIT_DCS_CMD(0xC9, 0x89),
_INIT_DCS_CMD(0xCA, 0x4E),
_INIT_DCS_CMD(0xCB, 0x00),
_INIT_DCS_CMD(0xA9, 0x3F),
_INIT_DCS_CMD(0xAA, 0x3E),
_INIT_DCS_CMD(0xAB, 0x3D),
_INIT_DCS_CMD(0xAC, 0x3C),
_INIT_DCS_CMD(0xAD, 0x3B),
_INIT_DCS_CMD(0xAE, 0x3A),
_INIT_DCS_CMD(0xAF, 0x39),
_INIT_DCS_CMD(0xB0, 0x38),
_INIT_DCS_CMD(0xFF, 0x27),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0xD0, 0x11),
_INIT_DCS_CMD(0xD1, 0x54),
_INIT_DCS_CMD(0xDE, 0x43),
_INIT_DCS_CMD(0xDF, 0x02),
_INIT_DCS_CMD(0xC0, 0x18),
_INIT_DCS_CMD(0xC1, 0x00),
_INIT_DCS_CMD(0xC2, 0x00),
_INIT_DCS_CMD(0x00, 0x00),
_INIT_DCS_CMD(0xC3, 0x00),
_INIT_DCS_CMD(0x56, 0x06),
_INIT_DCS_CMD(0x58, 0x80),
_INIT_DCS_CMD(0x59, 0x78),
_INIT_DCS_CMD(0x5A, 0x00),
_INIT_DCS_CMD(0x5B, 0x18),
_INIT_DCS_CMD(0x5C, 0x00),
_INIT_DCS_CMD(0x5D, 0x01),
_INIT_DCS_CMD(0x5E, 0x20),
_INIT_DCS_CMD(0x5F, 0x10),
_INIT_DCS_CMD(0x60, 0x00),
_INIT_DCS_CMD(0x61, 0x1C),
_INIT_DCS_CMD(0x62, 0x00),
_INIT_DCS_CMD(0x63, 0x01),
_INIT_DCS_CMD(0x64, 0x44),
_INIT_DCS_CMD(0x65, 0x1B),
_INIT_DCS_CMD(0x66, 0x00),
_INIT_DCS_CMD(0x67, 0x01),
_INIT_DCS_CMD(0x68, 0x44),
_INIT_DCS_CMD(0x98, 0x01),
_INIT_DCS_CMD(0xB4, 0x03),
_INIT_DCS_CMD(0x9B, 0xBE),
_INIT_DCS_CMD(0xAB, 0x14),
_INIT_DCS_CMD(0xBC, 0x08),
_INIT_DCS_CMD(0xBD, 0x28),
_INIT_DCS_CMD(0xFF, 0x2A),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x22, 0x2F),
_INIT_DCS_CMD(0x23, 0x08),
_INIT_DCS_CMD(0x24, 0x00),
_INIT_DCS_CMD(0x25, 0x62),
_INIT_DCS_CMD(0x26, 0xF8),
_INIT_DCS_CMD(0x27, 0x00),
_INIT_DCS_CMD(0x28, 0x1A),
_INIT_DCS_CMD(0x29, 0x00),
_INIT_DCS_CMD(0x2A, 0x1A),
_INIT_DCS_CMD(0x2B, 0x00),
_INIT_DCS_CMD(0x2D, 0x1A),
_INIT_DCS_CMD(0x64, 0x96),
_INIT_DCS_CMD(0x65, 0x10),
_INIT_DCS_CMD(0x66, 0x00),
_INIT_DCS_CMD(0x67, 0x96),
_INIT_DCS_CMD(0x68, 0x10),
_INIT_DCS_CMD(0x69, 0x00),
_INIT_DCS_CMD(0x6A, 0x96),
_INIT_DCS_CMD(0x6B, 0x10),
_INIT_DCS_CMD(0x6C, 0x00),
_INIT_DCS_CMD(0x70, 0x92),
_INIT_DCS_CMD(0x71, 0x10),
_INIT_DCS_CMD(0x72, 0x00),
_INIT_DCS_CMD(0x79, 0x96),
_INIT_DCS_CMD(0x7A, 0x10),
_INIT_DCS_CMD(0x88, 0x96),
_INIT_DCS_CMD(0x89, 0x10),
_INIT_DCS_CMD(0xA2, 0x3F),
_INIT_DCS_CMD(0xA3, 0x30),
_INIT_DCS_CMD(0xA4, 0xC0),
_INIT_DCS_CMD(0xA5, 0x03),
_INIT_DCS_CMD(0xE8, 0x00),
_INIT_DCS_CMD(0x97, 0x3C),
_INIT_DCS_CMD(0x98, 0x02),
_INIT_DCS_CMD(0x99, 0x95),
_INIT_DCS_CMD(0x9A, 0x06),
_INIT_DCS_CMD(0x9B, 0x00),
_INIT_DCS_CMD(0x9C, 0x0B),
_INIT_DCS_CMD(0x9D, 0x0A),
_INIT_DCS_CMD(0x9E, 0x90),
_INIT_DCS_CMD(0xFF, 0x25),
_INIT_DCS_CMD(0x13, 0x02),
_INIT_DCS_CMD(0x14, 0xD7),
_INIT_DCS_CMD(0xDB, 0x02),
_INIT_DCS_CMD(0xDC, 0xD7),
_INIT_DCS_CMD(0x17, 0xCF),
_INIT_DCS_CMD(0x19, 0x0F),
_INIT_DCS_CMD(0x1B, 0x5B),
_INIT_DCS_CMD(0xFF, 0x20),
_INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E),
_INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA),
_INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51),
_INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
_INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84),
_INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE),
_INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51),
_INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
_INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89),
_INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1),
_INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53),
_INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2),
_INIT_DCS_CMD(0xFF, 0x21),
_INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E),
_INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA),
_INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51),
_INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
_INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84),
_INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE),
_INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51),
_INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
_INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89),
_INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1),
_INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53),
_INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA),
_INIT_DCS_CMD(0xFF, 0xF0),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0x3A, 0x08),
_INIT_DCS_CMD(0xFF, 0x10),
_INIT_DCS_CMD(0xB9, 0x01),
_INIT_DCS_CMD(0xFF, 0x20),
_INIT_DCS_CMD(0x18, 0x40),
_INIT_DCS_CMD(0xFF, 0x10),
_INIT_DCS_CMD(0xB9, 0x02),
_INIT_DCS_CMD(0xFF, 0x10),
_INIT_DCS_CMD(0xFB, 0x01),
_INIT_DCS_CMD(0xB0, 0x01),
_INIT_DCS_CMD(0x35, 0x00),
_INIT_DCS_CMD(0x3B, 0x03, 0xAE, 0x1A, 0x04, 0x04),
_INIT_DELAY_CMD(100),
_INIT_DCS_CMD(0x11),
_INIT_DELAY_CMD(200),
_INIT_DCS_CMD(0x29),
_INIT_DELAY_CMD(100),
{},
};
static const struct panel_init_cmd boe_init_cmd[] = {
_INIT_DCS_CMD(0xB0, 0x05),
_INIT_DCS_CMD(0xB1, 0xE5),
_INIT_DCS_CMD(0xB3, 0x52),
_INIT_DCS_CMD(0xB0, 0x00),
_INIT_DCS_CMD(0xB3, 0x88),
_INIT_DCS_CMD(0xB0, 0x04),
_INIT_DCS_CMD(0xB8, 0x00),
_INIT_DCS_CMD(0xB0, 0x00),
_INIT_DCS_CMD(0xB6, 0x03),
_INIT_DCS_CMD(0xBA, 0x8B),
_INIT_DCS_CMD(0xBF, 0x1A),
_INIT_DCS_CMD(0xC0, 0x0F),
_INIT_DCS_CMD(0xC2, 0x0C),
_INIT_DCS_CMD(0xC3, 0x02),
_INIT_DCS_CMD(0xC4, 0x0C),
_INIT_DCS_CMD(0xC5, 0x02),
_INIT_DCS_CMD(0xB0, 0x01),
_INIT_DCS_CMD(0xE0, 0x26),
_INIT_DCS_CMD(0xE1, 0x26),
_INIT_DCS_CMD(0xDC, 0x00),
_INIT_DCS_CMD(0xDD, 0x00),
_INIT_DCS_CMD(0xCC, 0x26),
_INIT_DCS_CMD(0xCD, 0x26),
_INIT_DCS_CMD(0xC8, 0x00),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xD2, 0x03),
_INIT_DCS_CMD(0xD3, 0x03),
_INIT_DCS_CMD(0xE6, 0x04),
_INIT_DCS_CMD(0xE7, 0x04),
_INIT_DCS_CMD(0xC4, 0x09),
_INIT_DCS_CMD(0xC5, 0x09),
_INIT_DCS_CMD(0xD8, 0x0A),
_INIT_DCS_CMD(0xD9, 0x0A),
_INIT_DCS_CMD(0xC2, 0x0B),
_INIT_DCS_CMD(0xC3, 0x0B),
_INIT_DCS_CMD(0xD6, 0x0C),
_INIT_DCS_CMD(0xD7, 0x0C),
_INIT_DCS_CMD(0xC0, 0x05),
_INIT_DCS_CMD(0xC1, 0x05),
_INIT_DCS_CMD(0xD4, 0x06),
_INIT_DCS_CMD(0xD5, 0x06),
_INIT_DCS_CMD(0xCA, 0x07),
_INIT_DCS_CMD(0xCB, 0x07),
_INIT_DCS_CMD(0xDE, 0x08),
_INIT_DCS_CMD(0xDF, 0x08),
_INIT_DCS_CMD(0xB0, 0x02),
_INIT_DCS_CMD(0xC0, 0x00),
_INIT_DCS_CMD(0xC1, 0x0D),
_INIT_DCS_CMD(0xC2, 0x17),
_INIT_DCS_CMD(0xC3, 0x26),
_INIT_DCS_CMD(0xC4, 0x31),
_INIT_DCS_CMD(0xC5, 0x1C),
_INIT_DCS_CMD(0xC6, 0x2C),
_INIT_DCS_CMD(0xC7, 0x33),
_INIT_DCS_CMD(0xC8, 0x31),
_INIT_DCS_CMD(0xC9, 0x37),
_INIT_DCS_CMD(0xCA, 0x37),
_INIT_DCS_CMD(0xCB, 0x37),
_INIT_DCS_CMD(0xCC, 0x39),
_INIT_DCS_CMD(0xCD, 0x2E),
_INIT_DCS_CMD(0xCE, 0x2F),
_INIT_DCS_CMD(0xCF, 0x2F),
_INIT_DCS_CMD(0xD0, 0x07),
_INIT_DCS_CMD(0xD2, 0x00),
_INIT_DCS_CMD(0xD3, 0x0D),
_INIT_DCS_CMD(0xD4, 0x17),
_INIT_DCS_CMD(0xD5, 0x26),
_INIT_DCS_CMD(0xD6, 0x31),
_INIT_DCS_CMD(0xD7, 0x3F),
_INIT_DCS_CMD(0xD8, 0x3F),
_INIT_DCS_CMD(0xD9, 0x3F),
_INIT_DCS_CMD(0xDA, 0x3F),
_INIT_DCS_CMD(0xDB, 0x37),
_INIT_DCS_CMD(0xDC, 0x37),
_INIT_DCS_CMD(0xDD, 0x37),
_INIT_DCS_CMD(0xDE, 0x39),
_INIT_DCS_CMD(0xDF, 0x2E),
_INIT_DCS_CMD(0xE0, 0x2F),
_INIT_DCS_CMD(0xE1, 0x2F),
_INIT_DCS_CMD(0xE2, 0x07),
_INIT_DCS_CMD(0xB0, 0x03),
_INIT_DCS_CMD(0xC8, 0x0B),
_INIT_DCS_CMD(0xC9, 0x07),
_INIT_DCS_CMD(0xC3, 0x00),
_INIT_DCS_CMD(0xE7, 0x00),
_INIT_DCS_CMD(0xC5, 0x2A),
_INIT_DCS_CMD(0xDE, 0x2A),
_INIT_DCS_CMD(0xCA, 0x43),
_INIT_DCS_CMD(0xC9, 0x07),
_INIT_DCS_CMD(0xE4, 0xC0),
_INIT_DCS_CMD(0xE5, 0x0D),
_INIT_DCS_CMD(0xCB, 0x00),
_INIT_DCS_CMD(0xB0, 0x06),
_INIT_DCS_CMD(0xB8, 0xA5),
_INIT_DCS_CMD(0xC0, 0xA5),
_INIT_DCS_CMD(0xC7, 0x0F),
_INIT_DCS_CMD(0xD5, 0x32),
_INIT_DCS_CMD(0xB8, 0x00),
_INIT_DCS_CMD(0xC0, 0x00),
_INIT_DCS_CMD(0xBC, 0x00),
_INIT_DCS_CMD(0xB0, 0x07),
_INIT_DCS_CMD(0xB1, 0x00),
_INIT_DCS_CMD(0xB2, 0x02),
_INIT_DCS_CMD(0xB3, 0x0F),
_INIT_DCS_CMD(0xB4, 0x25),
_INIT_DCS_CMD(0xB5, 0x39),
_INIT_DCS_CMD(0xB6, 0x4E),
_INIT_DCS_CMD(0xB7, 0x72),
_INIT_DCS_CMD(0xB8, 0x97),
_INIT_DCS_CMD(0xB9, 0xDC),
_INIT_DCS_CMD(0xBA, 0x22),
_INIT_DCS_CMD(0xBB, 0xA4),
_INIT_DCS_CMD(0xBC, 0x2B),
_INIT_DCS_CMD(0xBD, 0x2F),
_INIT_DCS_CMD(0xBE, 0xA9),
_INIT_DCS_CMD(0xBF, 0x25),
_INIT_DCS_CMD(0xC0, 0x61),
_INIT_DCS_CMD(0xC1, 0x97),
_INIT_DCS_CMD(0xC2, 0xB2),
_INIT_DCS_CMD(0xC3, 0xCD),
_INIT_DCS_CMD(0xC4, 0xD9),
_INIT_DCS_CMD(0xC5, 0xE7),
_INIT_DCS_CMD(0xC6, 0xF4),
_INIT_DCS_CMD(0xC7, 0xFA),
_INIT_DCS_CMD(0xC8, 0xFC),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xCA, 0x00),
_INIT_DCS_CMD(0xCB, 0x16),
_INIT_DCS_CMD(0xCC, 0xAF),
_INIT_DCS_CMD(0xCD, 0xFF),
_INIT_DCS_CMD(0xCE, 0xFF),
_INIT_DCS_CMD(0xB0, 0x08),
_INIT_DCS_CMD(0xB1, 0x04),
_INIT_DCS_CMD(0xB2, 0x05),
_INIT_DCS_CMD(0xB3, 0x11),
_INIT_DCS_CMD(0xB4, 0x24),
_INIT_DCS_CMD(0xB5, 0x39),
_INIT_DCS_CMD(0xB6, 0x4F),
_INIT_DCS_CMD(0xB7, 0x72),
_INIT_DCS_CMD(0xB8, 0x98),
_INIT_DCS_CMD(0xB9, 0xDC),
_INIT_DCS_CMD(0xBA, 0x23),
_INIT_DCS_CMD(0xBB, 0xA6),
_INIT_DCS_CMD(0xBC, 0x2C),
_INIT_DCS_CMD(0xBD, 0x30),
_INIT_DCS_CMD(0xBE, 0xAA),
_INIT_DCS_CMD(0xBF, 0x26),
_INIT_DCS_CMD(0xC0, 0x62),
_INIT_DCS_CMD(0xC1, 0x9B),
_INIT_DCS_CMD(0xC2, 0xB5),
_INIT_DCS_CMD(0xC3, 0xCF),
_INIT_DCS_CMD(0xC4, 0xDB),
_INIT_DCS_CMD(0xC5, 0xE8),
_INIT_DCS_CMD(0xC6, 0xF5),
_INIT_DCS_CMD(0xC7, 0xFA),
_INIT_DCS_CMD(0xC8, 0xFC),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xCA, 0x00),
_INIT_DCS_CMD(0xCB, 0x16),
_INIT_DCS_CMD(0xCC, 0xAF),
_INIT_DCS_CMD(0xCD, 0xFF),
_INIT_DCS_CMD(0xCE, 0xFF),
_INIT_DCS_CMD(0xB0, 0x09),
_INIT_DCS_CMD(0xB1, 0x04),
_INIT_DCS_CMD(0xB2, 0x02),
_INIT_DCS_CMD(0xB3, 0x16),
_INIT_DCS_CMD(0xB4, 0x24),
_INIT_DCS_CMD(0xB5, 0x3B),
_INIT_DCS_CMD(0xB6, 0x4F),
_INIT_DCS_CMD(0xB7, 0x73),
_INIT_DCS_CMD(0xB8, 0x99),
_INIT_DCS_CMD(0xB9, 0xE0),
_INIT_DCS_CMD(0xBA, 0x26),
_INIT_DCS_CMD(0xBB, 0xAD),
_INIT_DCS_CMD(0xBC, 0x36),
_INIT_DCS_CMD(0xBD, 0x3A),
_INIT_DCS_CMD(0xBE, 0xAE),
_INIT_DCS_CMD(0xBF, 0x2A),
_INIT_DCS_CMD(0xC0, 0x66),
_INIT_DCS_CMD(0xC1, 0x9E),
_INIT_DCS_CMD(0xC2, 0xB8),
_INIT_DCS_CMD(0xC3, 0xD1),
_INIT_DCS_CMD(0xC4, 0xDD),
_INIT_DCS_CMD(0xC5, 0xE9),
_INIT_DCS_CMD(0xC6, 0xF6),
_INIT_DCS_CMD(0xC7, 0xFA),
_INIT_DCS_CMD(0xC8, 0xFC),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xCA, 0x00),
_INIT_DCS_CMD(0xCB, 0x16),
_INIT_DCS_CMD(0xCC, 0xAF),
_INIT_DCS_CMD(0xCD, 0xFF),
_INIT_DCS_CMD(0xCE, 0xFF),
_INIT_DCS_CMD(0xB0, 0x0A),
_INIT_DCS_CMD(0xB1, 0x00),
_INIT_DCS_CMD(0xB2, 0x02),
_INIT_DCS_CMD(0xB3, 0x0F),
_INIT_DCS_CMD(0xB4, 0x25),
_INIT_DCS_CMD(0xB5, 0x39),
_INIT_DCS_CMD(0xB6, 0x4E),
_INIT_DCS_CMD(0xB7, 0x72),
_INIT_DCS_CMD(0xB8, 0x97),
_INIT_DCS_CMD(0xB9, 0xDC),
_INIT_DCS_CMD(0xBA, 0x22),
_INIT_DCS_CMD(0xBB, 0xA4),
_INIT_DCS_CMD(0xBC, 0x2B),
_INIT_DCS_CMD(0xBD, 0x2F),
_INIT_DCS_CMD(0xBE, 0xA9),
_INIT_DCS_CMD(0xBF, 0x25),
_INIT_DCS_CMD(0xC0, 0x61),
_INIT_DCS_CMD(0xC1, 0x97),
_INIT_DCS_CMD(0xC2, 0xB2),
_INIT_DCS_CMD(0xC3, 0xCD),
_INIT_DCS_CMD(0xC4, 0xD9),
_INIT_DCS_CMD(0xC5, 0xE7),
_INIT_DCS_CMD(0xC6, 0xF4),
_INIT_DCS_CMD(0xC7, 0xFA),
_INIT_DCS_CMD(0xC8, 0xFC),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xCA, 0x00),
_INIT_DCS_CMD(0xCB, 0x16),
_INIT_DCS_CMD(0xCC, 0xAF),
_INIT_DCS_CMD(0xCD, 0xFF),
_INIT_DCS_CMD(0xCE, 0xFF),
_INIT_DCS_CMD(0xB0, 0x0B),
_INIT_DCS_CMD(0xB1, 0x04),
_INIT_DCS_CMD(0xB2, 0x05),
_INIT_DCS_CMD(0xB3, 0x11),
_INIT_DCS_CMD(0xB4, 0x24),
_INIT_DCS_CMD(0xB5, 0x39),
_INIT_DCS_CMD(0xB6, 0x4F),
_INIT_DCS_CMD(0xB7, 0x72),
_INIT_DCS_CMD(0xB8, 0x98),
_INIT_DCS_CMD(0xB9, 0xDC),
_INIT_DCS_CMD(0xBA, 0x23),
_INIT_DCS_CMD(0xBB, 0xA6),
_INIT_DCS_CMD(0xBC, 0x2C),
_INIT_DCS_CMD(0xBD, 0x30),
_INIT_DCS_CMD(0xBE, 0xAA),
_INIT_DCS_CMD(0xBF, 0x26),
_INIT_DCS_CMD(0xC0, 0x62),
_INIT_DCS_CMD(0xC1, 0x9B),
_INIT_DCS_CMD(0xC2, 0xB5),
_INIT_DCS_CMD(0xC3, 0xCF),
_INIT_DCS_CMD(0xC4, 0xDB),
_INIT_DCS_CMD(0xC5, 0xE8),
_INIT_DCS_CMD(0xC6, 0xF5),
_INIT_DCS_CMD(0xC7, 0xFA),
_INIT_DCS_CMD(0xC8, 0xFC),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xCA, 0x00),
_INIT_DCS_CMD(0xCB, 0x16),
_INIT_DCS_CMD(0xCC, 0xAF),
_INIT_DCS_CMD(0xCD, 0xFF),
_INIT_DCS_CMD(0xCE, 0xFF),
_INIT_DCS_CMD(0xB0, 0x0C),
_INIT_DCS_CMD(0xB1, 0x04),
_INIT_DCS_CMD(0xB2, 0x02),
_INIT_DCS_CMD(0xB3, 0x16),
_INIT_DCS_CMD(0xB4, 0x24),
_INIT_DCS_CMD(0xB5, 0x3B),
_INIT_DCS_CMD(0xB6, 0x4F),
_INIT_DCS_CMD(0xB7, 0x73),
_INIT_DCS_CMD(0xB8, 0x99),
_INIT_DCS_CMD(0xB9, 0xE0),
_INIT_DCS_CMD(0xBA, 0x26),
_INIT_DCS_CMD(0xBB, 0xAD),
_INIT_DCS_CMD(0xBC, 0x36),
_INIT_DCS_CMD(0xBD, 0x3A),
_INIT_DCS_CMD(0xBE, 0xAE),
_INIT_DCS_CMD(0xBF, 0x2A),
_INIT_DCS_CMD(0xC0, 0x66),
_INIT_DCS_CMD(0xC1, 0x9E),
_INIT_DCS_CMD(0xC2, 0xB8),
_INIT_DCS_CMD(0xC3, 0xD1),
_INIT_DCS_CMD(0xC4, 0xDD),
_INIT_DCS_CMD(0xC5, 0xE9),
_INIT_DCS_CMD(0xC6, 0xF6),
_INIT_DCS_CMD(0xC7, 0xFA),
_INIT_DCS_CMD(0xC8, 0xFC),
_INIT_DCS_CMD(0xC9, 0x00),
_INIT_DCS_CMD(0xCA, 0x00),
_INIT_DCS_CMD(0xCB, 0x16),
_INIT_DCS_CMD(0xCC, 0xAF),
_INIT_DCS_CMD(0xCD, 0xFF),
_INIT_DCS_CMD(0xCE, 0xFF),
_INIT_DCS_CMD(0xB0, 0x00),
_INIT_DCS_CMD(0xB3, 0x08),
_INIT_DCS_CMD(0xB0, 0x04),
_INIT_DCS_CMD(0xB8, 0x68),
_INIT_DELAY_CMD(150),
{},
};
static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = {
_INIT_DELAY_CMD(24),
_INIT_DCS_CMD(0x11),
_INIT_DELAY_CMD(120),
_INIT_DCS_CMD(0x29),
_INIT_DELAY_CMD(120),
{},
};
static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = {
_INIT_DELAY_CMD(24),
_INIT_DCS_CMD(0xB0, 0x01),
_INIT_DCS_CMD(0xC0, 0x48),
_INIT_DCS_CMD(0xC1, 0x48),
_INIT_DCS_CMD(0xC2, 0x47),
_INIT_DCS_CMD(0xC3, 0x47),
_INIT_DCS_CMD(0xC4, 0x46),
_INIT_DCS_CMD(0xC5, 0x46),
_INIT_DCS_CMD(0xC6, 0x45),
_INIT_DCS_CMD(0xC7, 0x45),
_INIT_DCS_CMD(0xC8, 0x64),
_INIT_DCS_CMD(0xC9, 0x64),
_INIT_DCS_CMD(0xCA, 0x4F),
_INIT_DCS_CMD(0xCB, 0x4F),
_INIT_DCS_CMD(0xCC, 0x40),
_INIT_DCS_CMD(0xCD, 0x40),
_INIT_DCS_CMD(0xCE, 0x66),
_INIT_DCS_CMD(0xCF, 0x66),
_INIT_DCS_CMD(0xD0, 0x4F),
_INIT_DCS_CMD(0xD1, 0x4F),
_INIT_DCS_CMD(0xD2, 0x41),
_INIT_DCS_CMD(0xD3, 0x41),
_INIT_DCS_CMD(0xD4, 0x48),
_INIT_DCS_CMD(0xD5, 0x48),
_INIT_DCS_CMD(0xD6, 0x47),
_INIT_DCS_CMD(0xD7, 0x47),
_INIT_DCS_CMD(0xD8, 0x46),
_INIT_DCS_CMD(0xD9, 0x46),
_INIT_DCS_CMD(0xDA, 0x45),
_INIT_DCS_CMD(0xDB, 0x45),
_INIT_DCS_CMD(0xDC, 0x64),
_INIT_DCS_CMD(0xDD, 0x64),
_INIT_DCS_CMD(0xDE, 0x4F),
_INIT_DCS_CMD(0xDF, 0x4F),
_INIT_DCS_CMD(0xE0, 0x40),
_INIT_DCS_CMD(0xE1, 0x40),
_INIT_DCS_CMD(0xE2, 0x66),
_INIT_DCS_CMD(0xE3, 0x66),
_INIT_DCS_CMD(0xE4, 0x4F),
_INIT_DCS_CMD(0xE5, 0x4F),
_INIT_DCS_CMD(0xE6, 0x41),
_INIT_DCS_CMD(0xE7, 0x41),
_INIT_DELAY_CMD(150),
{},
};
static const struct panel_init_cmd starry_qfh032011_53g_init_cmd[] = {
_INIT_DCS_CMD(0xB0, 0x01),
_INIT_DCS_CMD(0xC3, 0x4F),
_INIT_DCS_CMD(0xC4, 0x40),
_INIT_DCS_CMD(0xC5, 0x40),
_INIT_DCS_CMD(0xC6, 0x40),
_INIT_DCS_CMD(0xC7, 0x40),
_INIT_DCS_CMD(0xC8, 0x4D),
_INIT_DCS_CMD(0xC9, 0x52),
_INIT_DCS_CMD(0xCA, 0x51),
_INIT_DCS_CMD(0xCD, 0x5D),
_INIT_DCS_CMD(0xCE, 0x5B),
_INIT_DCS_CMD(0xCF, 0x4B),
_INIT_DCS_CMD(0xD0, 0x49),
_INIT_DCS_CMD(0xD1, 0x47),
_INIT_DCS_CMD(0xD2, 0x45),
_INIT_DCS_CMD(0xD3, 0x41),
_INIT_DCS_CMD(0xD7, 0x50),
_INIT_DCS_CMD(0xD8, 0x40),
_INIT_DCS_CMD(0xD9, 0x40),
_INIT_DCS_CMD(0xDA, 0x40),
_INIT_DCS_CMD(0xDB, 0x40),
_INIT_DCS_CMD(0xDC, 0x4E),
_INIT_DCS_CMD(0xDD, 0x52),
_INIT_DCS_CMD(0xDE, 0x51),
_INIT_DCS_CMD(0xE1, 0x5E),
_INIT_DCS_CMD(0xE2, 0x5C),
_INIT_DCS_CMD(0xE3, 0x4C),
_INIT_DCS_CMD(0xE4, 0x4A),
_INIT_DCS_CMD(0xE5, 0x48),
_INIT_DCS_CMD(0xE6, 0x46),
_INIT_DCS_CMD(0xE7, 0x42),
_INIT_DCS_CMD(0xB0, 0x03),
_INIT_DCS_CMD(0xBE, 0x03),
_INIT_DCS_CMD(0xCC, 0x44),
_INIT_DCS_CMD(0xC8, 0x07),
_INIT_DCS_CMD(0xC9, 0x05),
_INIT_DCS_CMD(0xCA, 0x42),
_INIT_DCS_CMD(0xCD, 0x3E),
_INIT_DCS_CMD(0xCF, 0x60),
_INIT_DCS_CMD(0xD2, 0x04),
_INIT_DCS_CMD(0xD3, 0x04),
_INIT_DCS_CMD(0xD4, 0x01),
_INIT_DCS_CMD(0xD5, 0x00),
_INIT_DCS_CMD(0xD6, 0x03),
_INIT_DCS_CMD(0xD7, 0x04),
_INIT_DCS_CMD(0xD9, 0x01),
_INIT_DCS_CMD(0xDB, 0x01),
_INIT_DCS_CMD(0xE4, 0xF0),
_INIT_DCS_CMD(0xE5, 0x0A),
_INIT_DCS_CMD(0xB0, 0x00),
_INIT_DCS_CMD(0xCC, 0x08),
_INIT_DCS_CMD(0xC2, 0x08),
_INIT_DCS_CMD(0xC4, 0x10),
_INIT_DCS_CMD(0xB0, 0x02),
_INIT_DCS_CMD(0xC0, 0x00),
_INIT_DCS_CMD(0xC1, 0x0A),
_INIT_DCS_CMD(0xC2, 0x20),
_INIT_DCS_CMD(0xC3, 0x24),
_INIT_DCS_CMD(0xC4, 0x23),
_INIT_DCS_CMD(0xC5, 0x29),
_INIT_DCS_CMD(0xC6, 0x23),
_INIT_DCS_CMD(0xC7, 0x1C),
_INIT_DCS_CMD(0xC8, 0x19),
_INIT_DCS_CMD(0xC9, 0x17),
_INIT_DCS_CMD(0xCA, 0x17),
_INIT_DCS_CMD(0xCB, 0x18),
_INIT_DCS_CMD(0xCC, 0x1A),
_INIT_DCS_CMD(0xCD, 0x1E),
_INIT_DCS_CMD(0xCE, 0x20),
_INIT_DCS_CMD(0xCF, 0x23),
_INIT_DCS_CMD(0xD0, 0x07),
_INIT_DCS_CMD(0xD1, 0x00),
_INIT_DCS_CMD(0xD2, 0x00),
_INIT_DCS_CMD(0xD3, 0x0A),
_INIT_DCS_CMD(0xD4, 0x13),
_INIT_DCS_CMD(0xD5, 0x1C),
_INIT_DCS_CMD(0xD6, 0x1A),
_INIT_DCS_CMD(0xD7, 0x13),
_INIT_DCS_CMD(0xD8, 0x17),
_INIT_DCS_CMD(0xD9, 0x1C),
_INIT_DCS_CMD(0xDA, 0x19),
_INIT_DCS_CMD(0xDB, 0x17),
_INIT_DCS_CMD(0xDC, 0x17),
_INIT_DCS_CMD(0xDD, 0x18),
_INIT_DCS_CMD(0xDE, 0x1A),
_INIT_DCS_CMD(0xDF, 0x1E),
_INIT_DCS_CMD(0xE0, 0x20),
_INIT_DCS_CMD(0xE1, 0x23),
_INIT_DCS_CMD(0xE2, 0x07),
_INIT_DCS_CMD(0X11),
_INIT_DELAY_CMD(120),
_INIT_DCS_CMD(0X29),
_INIT_DELAY_CMD(80),
{},
};
static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = {
_INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
_INIT_DCS_CMD(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x31, 0xD7, 0x2F, 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11,
0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x74, 0x33),
_INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x72, 0x3C, 0xA3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xF5),
_INIT_DCS_CMD(0xB4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5C, 0x63, 0x5C, 0x01, 0x9E),
_INIT_DCS_CMD(0xE9, 0xCD),
_INIT_DCS_CMD(0xBA, 0x84),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xBC, 0x1B, 0x04),
_INIT_DCS_CMD(0xBE, 0x20),
_INIT_DCS_CMD(0xBF, 0xFC, 0xC4),
_INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xA0, 0x61, 0x08, 0xF5, 0x03),
_INIT_DCS_CMD(0xE9, 0xCC),
_INIT_DCS_CMD(0xC7, 0x80),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xE9, 0xC6),
_INIT_DCS_CMD(0xC8, 0x97),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01),
_INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x33),
_INIT_DCS_CMD(0xCC, 0x02),
_INIT_DCS_CMD(0xE9, 0xC4),
_INIT_DCS_CMD(0xD0, 0x03),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF),
_INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F),
_INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3B, 0x12, 0x12, 0x03,
0x03, 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x17, 0x94, 0x07, 0x94, 0x00, 0x00),
_INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1A, 0x1A,
0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
_INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1A, 0x1A,
0x1B, 0x1B, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
_INIT_DCS_CMD(0xD8, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA,
0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0),
_INIT_DCS_CMD(0xE0, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB,
0xAB, 0x55, 0x5C, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 0xAB, 0x55, 0x5C, 0x68, 0x73),
_INIT_DCS_CMD(0xE7, 0x0E, 0x10, 0x10, 0x21, 0x2B, 0x9A, 0x02, 0x54, 0x9A, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10),
_INIT_DCS_CMD(0xBD, 0x01),
_INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11),
_INIT_DCS_CMD(0xCB, 0x86),
_INIT_DCS_CMD(0xD2, 0x3C, 0xFA),
_INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01),
_INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40),
_INIT_DCS_CMD(0xBD, 0x02),
_INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0),
_INIT_DCS_CMD(0xE7, 0xFE, 0x04, 0xFE, 0x04, 0xFE, 0x04, 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00),
_INIT_DCS_CMD(0xBD, 0x03),
_INIT_DCS_CMD(0xE9, 0xC6),
_INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xD8, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8,
0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00),
_INIT_DCS_CMD(0xBD, 0x00),
_INIT_DCS_CMD(0xE9, 0xC4),
_INIT_DCS_CMD(0xBA, 0x96),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xBD, 0x01),
_INIT_DCS_CMD(0xE9, 0xC5),
_INIT_DCS_CMD(0xBA, 0x4F),
_INIT_DCS_CMD(0xE9, 0x3F),
_INIT_DCS_CMD(0xBD, 0x00),
_INIT_DCS_CMD(0x11),
_INIT_DELAY_CMD(120),
_INIT_DCS_CMD(0x29),
{},
};
static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
{
return container_of(panel, struct boe_panel, base);
}
static int boe_panel_init_dcs_cmd(struct boe_panel *boe)
{
struct mipi_dsi_device *dsi = boe->dsi;
struct drm_panel *panel = &boe->base;
int i, err = 0;
if (boe->desc->init_cmds) {
const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
for (i = 0; init_cmds[i].len != 0; i++) {
const struct panel_init_cmd *cmd = &init_cmds[i];
switch (cmd->type) {
case DELAY_CMD:
msleep(cmd->data[0]);
err = 0;
break;
case INIT_DCS_CMD:
err = mipi_dsi_dcs_write(dsi, cmd->data[0],
cmd->len <= 1 ? NULL :
&cmd->data[1],
cmd->len - 1);
break;
default:
err = -EINVAL;
}
if (err < 0) {
dev_err(panel->dev,
"failed to write command %u\n", i);
return err;
}
}
}
return 0;
}
static int boe_panel_enter_sleep_mode(struct boe_panel *boe)
{
struct mipi_dsi_device *dsi = boe->dsi;
int ret;
dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
ret = mipi_dsi_dcs_set_display_off(dsi);
if (ret < 0)
return ret;
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
if (ret < 0)
return ret;
return 0;
}
static int boe_panel_disable(struct drm_panel *panel)
{
struct boe_panel *boe = to_boe_panel(panel);
int ret;
ret = boe_panel_enter_sleep_mode(boe);
if (ret < 0) {
dev_err(panel->dev, "failed to set panel off: %d\n", ret);
return ret;
}
msleep(150);
return 0;
}
static int boe_panel_unprepare(struct drm_panel *panel)
{
struct boe_panel *boe = to_boe_panel(panel);
if (!boe->prepared)
return 0;
if (boe->desc->discharge_on_disable) {
regulator_disable(boe->avee);
regulator_disable(boe->avdd);
usleep_range(5000, 7000);
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(5000, 7000);
regulator_disable(boe->pp1800);
regulator_disable(boe->pp3300);
} else {
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(1000, 2000);
regulator_disable(boe->avee);
regulator_disable(boe->avdd);
usleep_range(5000, 7000);
regulator_disable(boe->pp1800);
regulator_disable(boe->pp3300);
}
boe->prepared = false;
return 0;
}
static int boe_panel_prepare(struct drm_panel *panel)
{
struct boe_panel *boe = to_boe_panel(panel);
int ret;
if (boe->prepared)
return 0;
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(1000, 1500);
ret = regulator_enable(boe->pp3300);
if (ret < 0)
return ret;
ret = regulator_enable(boe->pp1800);
if (ret < 0)
return ret;
usleep_range(3000, 5000);
ret = regulator_enable(boe->avdd);
if (ret < 0)
goto poweroff1v8;
ret = regulator_enable(boe->avee);
if (ret < 0)
goto poweroffavdd;
usleep_range(10000, 11000);
if (boe->desc->lp11_before_reset) {
mipi_dsi_dcs_nop(boe->dsi);
usleep_range(1000, 2000);
}
gpiod_set_value(boe->enable_gpio, 1);
usleep_range(1000, 2000);
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(1000, 2000);
gpiod_set_value(boe->enable_gpio, 1);
usleep_range(6000, 10000);
ret = boe_panel_init_dcs_cmd(boe);
if (ret < 0) {
dev_err(panel->dev, "failed to init panel: %d\n", ret);
goto poweroff;
}
boe->prepared = true;
return 0;
poweroff:
regulator_disable(boe->avee);
poweroffavdd:
regulator_disable(boe->avdd);
poweroff1v8:
usleep_range(5000, 7000);
regulator_disable(boe->pp1800);
gpiod_set_value(boe->enable_gpio, 0);
return ret;
}
static int boe_panel_enable(struct drm_panel *panel)
{
msleep(130);
return 0;
}
static const struct drm_display_mode boe_tv110c9m_default_mode = {
.clock = 166594,
.hdisplay = 1200,
.hsync_start = 1200 + 40,
.hsync_end = 1200 + 40 + 8,
.htotal = 1200 + 40 + 8 + 28,
.vdisplay = 2000,
.vsync_start = 2000 + 26,
.vsync_end = 2000 + 26 + 2,
.vtotal = 2000 + 26 + 2 + 148,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc boe_tv110c9m_desc = {
.modes = &boe_tv110c9m_default_mode,
.bpc = 8,
.size = {
.width_mm = 143,
.height_mm = 238,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO
| MIPI_DSI_MODE_VIDEO_HSE
| MIPI_DSI_CLOCK_NON_CONTINUOUS
| MIPI_DSI_MODE_VIDEO_BURST,
.init_cmds = boe_tv110c9m_init_cmd,
};
static const struct drm_display_mode inx_hj110iz_default_mode = {
.clock = 168432,
.hdisplay = 1200,
.hsync_start = 1200 + 40,
.hsync_end = 1200 + 40 + 8,
.htotal = 1200 + 40 + 8 + 28,
.vdisplay = 2000,
.vsync_start = 2000 + 26,
.vsync_end = 2000 + 26 + 2,
.vtotal = 2000 + 26 + 2 + 172,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc inx_hj110iz_desc = {
.modes = &inx_hj110iz_default_mode,
.bpc = 8,
.size = {
.width_mm = 143,
.height_mm = 238,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO
| MIPI_DSI_MODE_VIDEO_HSE
| MIPI_DSI_CLOCK_NON_CONTINUOUS
| MIPI_DSI_MODE_VIDEO_BURST,
.init_cmds = inx_hj110iz_init_cmd,
};
static const struct drm_display_mode boe_tv101wum_nl6_default_mode = {
.clock = 159425,
.hdisplay = 1200,
.hsync_start = 1200 + 100,
.hsync_end = 1200 + 100 + 40,
.htotal = 1200 + 100 + 40 + 24,
.vdisplay = 1920,
.vsync_start = 1920 + 10,
.vsync_end = 1920 + 10 + 14,
.vtotal = 1920 + 10 + 14 + 4,
};
static const struct panel_desc boe_tv101wum_nl6_desc = {
.modes = &boe_tv101wum_nl6_default_mode,
.bpc = 8,
.size = {
.width_mm = 135,
.height_mm = 216,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = boe_init_cmd,
.discharge_on_disable = false,
};
static const struct drm_display_mode auo_kd101n80_45na_default_mode = {
.clock = 157000,
.hdisplay = 1200,
.hsync_start = 1200 + 60,
.hsync_end = 1200 + 60 + 24,
.htotal = 1200 + 60 + 24 + 56,
.vdisplay = 1920,
.vsync_start = 1920 + 16,
.vsync_end = 1920 + 16 + 4,
.vtotal = 1920 + 16 + 4 + 16,
};
static const struct panel_desc auo_kd101n80_45na_desc = {
.modes = &auo_kd101n80_45na_default_mode,
.bpc = 8,
.size = {
.width_mm = 135,
.height_mm = 216,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = auo_kd101n80_45na_init_cmd,
.discharge_on_disable = true,
};
static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
.clock = 159916,
.hdisplay = 1200,
.hsync_start = 1200 + 80,
.hsync_end = 1200 + 80 + 24,
.htotal = 1200 + 80 + 24 + 60,
.vdisplay = 1920,
.vsync_start = 1920 + 20,
.vsync_end = 1920 + 20 + 4,
.vtotal = 1920 + 20 + 4 + 10,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc boe_tv101wum_n53_desc = {
.modes = &boe_tv101wum_n53_default_mode,
.bpc = 8,
.size = {
.width_mm = 135,
.height_mm = 216,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = boe_init_cmd,
};
static const struct drm_display_mode auo_b101uan08_3_default_mode = {
.clock = 159667,
.hdisplay = 1200,
.hsync_start = 1200 + 60,
.hsync_end = 1200 + 60 + 4,
.htotal = 1200 + 60 + 4 + 80,
.vdisplay = 1920,
.vsync_start = 1920 + 34,
.vsync_end = 1920 + 34 + 2,
.vtotal = 1920 + 34 + 2 + 24,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc auo_b101uan08_3_desc = {
.modes = &auo_b101uan08_3_default_mode,
.bpc = 8,
.size = {
.width_mm = 135,
.height_mm = 216,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = auo_b101uan08_3_init_cmd,
.lp11_before_reset = true,
};
static const struct drm_display_mode boe_tv105wum_nw0_default_mode = {
.clock = 159916,
.hdisplay = 1200,
.hsync_start = 1200 + 80,
.hsync_end = 1200 + 80 + 24,
.htotal = 1200 + 80 + 24 + 60,
.vdisplay = 1920,
.vsync_start = 1920 + 20,
.vsync_end = 1920 + 20 + 4,
.vtotal = 1920 + 20 + 4 + 10,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc boe_tv105wum_nw0_desc = {
.modes = &boe_tv105wum_nw0_default_mode,
.bpc = 8,
.size = {
.width_mm = 141,
.height_mm = 226,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = boe_init_cmd,
.lp11_before_reset = true,
};
static const struct drm_display_mode starry_qfh032011_53g_default_mode = {
.clock = 165731,
.hdisplay = 1200,
.hsync_start = 1200 + 100,
.hsync_end = 1200 + 100 + 10,
.htotal = 1200 + 100 + 10 + 100,
.vdisplay = 1920,
.vsync_start = 1920 + 14,
.vsync_end = 1920 + 14 + 10,
.vtotal = 1920 + 14 + 10 + 15,
};
static const struct panel_desc starry_qfh032011_53g_desc = {
.modes = &starry_qfh032011_53g_default_mode,
.bpc = 8,
.size = {
.width_mm = 135,
.height_mm = 216,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = starry_qfh032011_53g_init_cmd,
.lp11_before_reset = true,
};
static const struct drm_display_mode starry_himax83102_j02_default_mode = {
.clock = 162680,
.hdisplay = 1200,
.hsync_start = 1200 + 60,
.hsync_end = 1200 + 60 + 20,
.htotal = 1200 + 60 + 20 + 40,
.vdisplay = 1920,
.vsync_start = 1920 + 116,
.vsync_end = 1920 + 116 + 8,
.vtotal = 1920 + 116 + 8 + 12,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc starry_himax83102_j02_desc = {
.modes = &starry_himax83102_j02_default_mode,
.bpc = 8,
.size = {
.width_mm = 141,
.height_mm = 226,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init_cmds = starry_himax83102_j02_init_cmd,
.lp11_before_reset = true,
};
static int boe_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct boe_panel *boe = to_boe_panel(panel);
const struct drm_display_mode *m = boe->desc->modes;
struct drm_display_mode *mode;
mode = drm_mode_duplicate(connector->dev, m);
if (!mode) {
dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
return -ENOMEM;
}
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_probed_add(connector, mode);
connector->display_info.width_mm = boe->desc->size.width_mm;
connector->display_info.height_mm = boe->desc->size.height_mm;
connector->display_info.bpc = boe->desc->bpc;
/*
* TODO: Remove once all drm drivers call
* drm_connector_set_orientation_from_panel()
*/
drm_connector_set_panel_orientation(connector, boe->orientation);
return 1;
}
static enum drm_panel_orientation boe_panel_get_orientation(struct drm_panel *panel)
{
struct boe_panel *boe = to_boe_panel(panel);
return boe->orientation;
}
static const struct drm_panel_funcs boe_panel_funcs = {
.disable = boe_panel_disable,
.unprepare = boe_panel_unprepare,
.prepare = boe_panel_prepare,
.enable = boe_panel_enable,
.get_modes = boe_panel_get_modes,
.get_orientation = boe_panel_get_orientation,
};
static int boe_panel_add(struct boe_panel *boe)
{
struct device *dev = &boe->dsi->dev;
int err;
boe->avdd = devm_regulator_get(dev, "avdd");
if (IS_ERR(boe->avdd))
return PTR_ERR(boe->avdd);
boe->avee = devm_regulator_get(dev, "avee");
if (IS_ERR(boe->avee))
return PTR_ERR(boe->avee);
boe->pp3300 = devm_regulator_get(dev, "pp3300");
if (IS_ERR(boe->pp3300))
return PTR_ERR(boe->pp3300);
boe->pp1800 = devm_regulator_get(dev, "pp1800");
if (IS_ERR(boe->pp1800))
return PTR_ERR(boe->pp1800);
boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(boe->enable_gpio)) {
dev_err(dev, "cannot get reset-gpios %ld\n",
PTR_ERR(boe->enable_gpio));
return PTR_ERR(boe->enable_gpio);
}
gpiod_set_value(boe->enable_gpio, 0);
boe->base.prepare_prev_first = true;
drm_panel_init(&boe->base, dev, &boe_panel_funcs,
DRM_MODE_CONNECTOR_DSI);
err = of_drm_get_panel_orientation(dev->of_node, &boe->orientation);
if (err < 0) {
dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
return err;
}
err = drm_panel_of_backlight(&boe->base);
if (err)
return err;
boe->base.funcs = &boe_panel_funcs;
boe->base.dev = &boe->dsi->dev;
drm_panel_add(&boe->base);
return 0;
}
static int boe_panel_probe(struct mipi_dsi_device *dsi)
{
struct boe_panel *boe;
int ret;
const struct panel_desc *desc;
boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
if (!boe)
return -ENOMEM;
desc = of_device_get_match_data(&dsi->dev);
dsi->lanes = desc->lanes;
dsi->format = desc->format;
dsi->mode_flags = desc->mode_flags;
boe->desc = desc;
boe->dsi = dsi;
ret = boe_panel_add(boe);
if (ret < 0)
return ret;
mipi_dsi_set_drvdata(dsi, boe);
ret = mipi_dsi_attach(dsi);
if (ret)
drm_panel_remove(&boe->base);
return ret;
}
static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
{
struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
drm_panel_disable(&boe->base);
drm_panel_unprepare(&boe->base);
}
static void boe_panel_remove(struct mipi_dsi_device *dsi)
{
struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
int ret;
boe_panel_shutdown(dsi);
ret = mipi_dsi_detach(dsi);
if (ret < 0)
dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
if (boe->base.dev)
drm_panel_remove(&boe->base);
}
static const struct of_device_id boe_of_match[] = {
{ .compatible = "boe,tv101wum-nl6",
.data = &boe_tv101wum_nl6_desc
},
{ .compatible = "auo,kd101n80-45na",
.data = &auo_kd101n80_45na_desc
},
{ .compatible = "boe,tv101wum-n53",
.data = &boe_tv101wum_n53_desc
},
{ .compatible = "auo,b101uan08.3",
.data = &auo_b101uan08_3_desc
},
{ .compatible = "boe,tv105wum-nw0",
.data = &boe_tv105wum_nw0_desc
},
{ .compatible = "boe,tv110c9m-ll3",
.data = &boe_tv110c9m_desc
},
{ .compatible = "innolux,hj110iz-01a",
.data = &inx_hj110iz_desc
},
{ .compatible = "starry,2081101qfh032011-53g",
.data = &starry_qfh032011_53g_desc
},
{ .compatible = "starry,himax83102-j02",
.data = &starry_himax83102_j02_desc
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, boe_of_match);
static struct mipi_dsi_driver boe_panel_driver = {
.driver = {
.name = "panel-boe-tv101wum-nl6",
.of_match_table = boe_of_match,
},
.probe = boe_panel_probe,
.remove = boe_panel_remove,
.shutdown = boe_panel_shutdown,
};
module_mipi_dsi_driver(boe_panel_driver);
MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
MODULE_LICENSE("GPL v2");