Rob Herring (Arm) a4a6e2078d perf: arm_pmuv3: Prepare for more than 32 counters ... Various PMUv3 registers which are a mask of counters are 64-bit registers, but the accessor functions take a u32. This has been fine as the upper 32-bits have been RES0 as there has been a maximum of 32 counters prior to Armv9.4/8.9. With Armv9.4/8.9, a 33rd counter is added. Update the accessor functions to use a u64 instead. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-2-280a8d7ff465@kernel.org Signed-off-by: Will Deacon <will@kernel.org>		2024-08-16 13:09:12 +01:00
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asm	perf: arm_pmuv3: Prepare for more than 32 counters	2024-08-16 13:09:12 +01:00
uapi/asm	arm64: generate 64-bit syscall.tbl	2024-07-10 14:23:38 +02:00