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ab65e04dc1
DE2/DE3 mixers have to run at specific frequency in order to work optimally. This wasn't actually possible for some SoCs because "de" clock wasn't allowed to adjust parent rate. Add CLK_SET_RATE_PARENT flag to all "de" clocks which didn't have it yet. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
592 lines
18 KiB
C
592 lines
18 KiB
C
/*
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* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*
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* Based on ccu-sun8i-h3.c, which is:
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* Copyright (c) 2016 Maxime Ripard. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_mult.h"
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#include "ccu_nk.h"
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#include "ccu_nkm.h"
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#include "ccu_nkmp.h"
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#include "ccu_nm.h"
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#include "ccu_phase.h"
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#include "ccu-sun8i-v3s.h"
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static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
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"osc24M", 0x000,
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8, 5, /* N */
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4, 2, /* K */
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0, 2, /* M */
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16, 2, /* P */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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* the base (2x, 4x and 8x), and one variable divider (the one true
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* pll audio).
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*
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* We don't have any need for the variable divider for now, so we just
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* hardcode it to match with the clock names
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*/
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#define SUN8I_V3S_PLL_AUDIO_REG 0x008
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static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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"osc24M", 0x008,
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8, 7, /* N */
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0, 5, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
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"osc24M", 0x0010,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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"osc24M", 0x0018,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
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"osc24M", 0x020,
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8, 5, /* N */
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4, 2, /* K */
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0, 2, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
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"osc24M", 0x028,
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8, 5, /* N */
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4, 2, /* K */
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BIT(31), /* gate */
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BIT(28), /* lock */
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2, /* post-div */
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0);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
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"osc24M", 0x002c,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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0);
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static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
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"osc24M", 0x044,
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8, 5, /* N */
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4, 2, /* K */
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BIT(31), /* gate */
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BIT(28), /* lock */
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2, /* post-div */
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0);
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static const char * const cpu_parents[] = { "osc32k", "osc24M",
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"pll-cpu", "pll-cpu" };
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static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
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0x050, 16, 2, CLK_IS_CRITICAL);
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static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
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static const char * const ahb1_parents[] = { "osc32k", "osc24M",
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"axi", "pll-periph0" };
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static const struct ccu_mux_var_prediv ahb1_predivs[] = {
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{ .index = 3, .shift = 6, .width = 2 },
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};
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static struct ccu_div ahb1_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 12,
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.width = 2,
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.var_predivs = ahb1_predivs,
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.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
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},
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.common = {
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.reg = 0x054,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("ahb1",
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ahb1_parents,
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&ccu_div_ops,
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0),
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},
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};
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static struct clk_div_table apb1_div_table[] = {
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{ .val = 0, .div = 2 },
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{ .val = 1, .div = 2 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 8 },
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{ /* Sentinel */ },
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};
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static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
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0x054, 8, 2, apb1_div_table, 0);
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static const char * const apb2_parents[] = { "osc32k", "osc24M",
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"pll-periph0", "pll-periph0" };
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static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
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0, 5, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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0);
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static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
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static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
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{ .index = 1, .div = 2 },
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};
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static struct ccu_mux ahb2_clk = {
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.mux = {
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.shift = 0,
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.width = 1,
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.fixed_predivs = ahb2_fixed_predivs,
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.n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
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},
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.common = {
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.reg = 0x05c,
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.features = CCU_FEATURE_FIXED_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("ahb2",
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ahb2_parents,
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&ccu_mux_ops,
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0),
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},
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};
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static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
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0x060, BIT(5), 0);
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static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
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0x060, BIT(6), 0);
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static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
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0x060, BIT(8), 0);
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static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
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0x060, BIT(9), 0);
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static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
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0x060, BIT(10), 0);
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static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
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0x060, BIT(14), 0);
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static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
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0x060, BIT(17), 0);
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static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
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0x060, BIT(19), 0);
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static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
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0x060, BIT(20), 0);
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static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
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0x060, BIT(24), 0);
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static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
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0x060, BIT(26), 0);
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static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
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0x060, BIT(29), 0);
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static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
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0x064, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
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0x064, BIT(4), 0);
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static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
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0x064, BIT(8), 0);
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static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
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0x064, BIT(12), 0);
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static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
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0x068, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
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0x068, BIT(5), 0);
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static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
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0x06c, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
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0x06c, BIT(1), 0);
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static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
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0x06c, BIT(16), 0);
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static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
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0x06c, BIT(17), 0);
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static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
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0x06c, BIT(18), 0);
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static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
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0x070, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
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0x070, BIT(7), 0);
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static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
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"pll-periph1" };
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static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
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0x088, 20, 3, 0);
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static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
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0x088, 8, 3, 0);
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static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
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0x08c, 20, 3, 0);
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static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
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0x08c, 8, 3, 0);
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static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
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0x090, 20, 3, 0);
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static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
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0x090, 8, 3, 0);
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static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
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static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
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0x0cc, BIT(8), 0);
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static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
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0x0cc, BIT(16), 0);
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static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
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static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
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0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
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static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
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0x100, BIT(0), 0);
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static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
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0x100, BIT(1), 0);
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static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram",
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0x100, BIT(17), 0);
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static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",
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0x100, BIT(18), 0);
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static const char * const de_parents[] = { "pll-video", "pll-periph0" };
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static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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0x104, 0, 4, 24, 2, BIT(31),
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CLK_SET_RATE_PARENT);
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static const char * const tcon_parents[] = { "pll-video" };
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
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0x118, 0, 4, 24, 3, BIT(31), 0);
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static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
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0x130, BIT(31), 0);
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static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
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"pll-periph0", "pll-periph1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
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0x130, 0, 5, 8, 3, BIT(15), 0);
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static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
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static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
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0x134, 16, 4, 24, 3, BIT(31), 0);
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static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
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0x134, 0, 5, 8, 3, BIT(15), 0);
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static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
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0x13c, 16, 3, BIT(31), 0);
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static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
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0x140, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
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0x144, BIT(31), 0);
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static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
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"pll-ddr" };
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static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
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0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
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static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
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"pll-isp" };
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static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
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0x16c, 0, 3, 24, 2, BIT(31), 0);
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static struct ccu_common *sun8i_v3s_ccu_clks[] = {
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&pll_cpu_clk.common,
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&pll_audio_base_clk.common,
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&pll_video_clk.common,
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&pll_ve_clk.common,
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&pll_ddr_clk.common,
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&pll_periph0_clk.common,
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&pll_isp_clk.common,
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&pll_periph1_clk.common,
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&cpu_clk.common,
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&axi_clk.common,
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&ahb1_clk.common,
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&apb1_clk.common,
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&apb2_clk.common,
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&ahb2_clk.common,
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&bus_ce_clk.common,
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&bus_dma_clk.common,
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&bus_mmc0_clk.common,
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&bus_mmc1_clk.common,
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&bus_mmc2_clk.common,
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&bus_dram_clk.common,
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&bus_emac_clk.common,
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&bus_hstimer_clk.common,
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&bus_spi0_clk.common,
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&bus_otg_clk.common,
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&bus_ehci0_clk.common,
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&bus_ohci0_clk.common,
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&bus_ve_clk.common,
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&bus_tcon0_clk.common,
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&bus_csi_clk.common,
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&bus_de_clk.common,
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&bus_codec_clk.common,
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&bus_pio_clk.common,
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&bus_i2c0_clk.common,
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&bus_i2c1_clk.common,
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&bus_uart0_clk.common,
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&bus_uart1_clk.common,
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&bus_uart2_clk.common,
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&bus_ephy_clk.common,
|
|
&bus_dbg_clk.common,
|
|
&mmc0_clk.common,
|
|
&mmc0_sample_clk.common,
|
|
&mmc0_output_clk.common,
|
|
&mmc1_clk.common,
|
|
&mmc1_sample_clk.common,
|
|
&mmc1_output_clk.common,
|
|
&mmc2_clk.common,
|
|
&mmc2_sample_clk.common,
|
|
&mmc2_output_clk.common,
|
|
&ce_clk.common,
|
|
&spi0_clk.common,
|
|
&usb_phy0_clk.common,
|
|
&usb_ohci0_clk.common,
|
|
&dram_clk.common,
|
|
&dram_ve_clk.common,
|
|
&dram_csi_clk.common,
|
|
&dram_ohci_clk.common,
|
|
&dram_ehci_clk.common,
|
|
&de_clk.common,
|
|
&tcon_clk.common,
|
|
&csi_misc_clk.common,
|
|
&csi0_mclk_clk.common,
|
|
&csi1_sclk_clk.common,
|
|
&csi1_mclk_clk.common,
|
|
&ve_clk.common,
|
|
&ac_dig_clk.common,
|
|
&avs_clk.common,
|
|
&mbus_clk.common,
|
|
&mipi_csi_clk.common,
|
|
};
|
|
|
|
/* We hardcode the divider to 4 for now */
|
|
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
|
|
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
|
|
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
|
|
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
|
|
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
|
|
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
|
|
static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
|
|
"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
|
|
static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
|
|
"pll-periph0", 1, 2, 0);
|
|
|
|
static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
|
|
.hws = {
|
|
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
|
|
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
|
|
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
|
|
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
|
|
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
|
|
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
|
|
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
|
|
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
|
|
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
|
|
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
|
|
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
|
|
[CLK_PLL_ISP] = &pll_isp_clk.common.hw,
|
|
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
|
|
[CLK_CPU] = &cpu_clk.common.hw,
|
|
[CLK_AXI] = &axi_clk.common.hw,
|
|
[CLK_AHB1] = &ahb1_clk.common.hw,
|
|
[CLK_APB1] = &apb1_clk.common.hw,
|
|
[CLK_APB2] = &apb2_clk.common.hw,
|
|
[CLK_AHB2] = &ahb2_clk.common.hw,
|
|
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
|
|
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
|
|
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
|
|
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
|
|
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
|
|
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
|
|
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
|
|
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
|
|
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
|
|
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
|
|
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
|
|
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
|
|
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
|
|
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
|
|
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
|
|
[CLK_BUS_DE] = &bus_de_clk.common.hw,
|
|
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
|
|
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
|
|
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
|
|
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
|
|
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
|
|
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
|
|
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
|
|
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
|
|
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
|
|
[CLK_MMC0] = &mmc0_clk.common.hw,
|
|
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
|
|
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
|
|
[CLK_MMC1] = &mmc1_clk.common.hw,
|
|
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
|
|
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
|
|
[CLK_CE] = &ce_clk.common.hw,
|
|
[CLK_SPI0] = &spi0_clk.common.hw,
|
|
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
|
|
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
|
|
[CLK_DRAM] = &dram_clk.common.hw,
|
|
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
|
|
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
|
|
[CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
|
|
[CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
|
|
[CLK_DE] = &de_clk.common.hw,
|
|
[CLK_TCON0] = &tcon_clk.common.hw,
|
|
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
|
|
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
|
|
[CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
|
|
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
|
|
[CLK_VE] = &ve_clk.common.hw,
|
|
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
|
|
[CLK_AVS] = &avs_clk.common.hw,
|
|
[CLK_MBUS] = &mbus_clk.common.hw,
|
|
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
|
|
},
|
|
.num = CLK_NUMBER,
|
|
};
|
|
|
|
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
|
|
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
|
|
|
|
[RST_MBUS] = { 0x0fc, BIT(31) },
|
|
|
|
[RST_BUS_CE] = { 0x2c0, BIT(5) },
|
|
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
|
|
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
|
|
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
|
|
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
|
|
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
|
|
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
|
|
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
|
|
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
|
|
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
|
|
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
|
|
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
|
|
|
|
[RST_BUS_VE] = { 0x2c4, BIT(0) },
|
|
[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
|
|
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
|
|
[RST_BUS_DE] = { 0x2c4, BIT(12) },
|
|
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
|
|
|
|
[RST_BUS_EPHY] = { 0x2c8, BIT(2) },
|
|
|
|
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
|
|
|
|
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
|
|
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
|
|
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
|
|
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
|
|
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
|
|
};
|
|
|
|
static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
|
|
.ccu_clks = sun8i_v3s_ccu_clks,
|
|
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
|
|
|
|
.hw_clks = &sun8i_v3s_hw_clks,
|
|
|
|
.resets = sun8i_v3s_ccu_resets,
|
|
.num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets),
|
|
};
|
|
|
|
static void __init sun8i_v3s_ccu_setup(struct device_node *node)
|
|
{
|
|
void __iomem *reg;
|
|
u32 val;
|
|
|
|
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
|
if (IS_ERR(reg)) {
|
|
pr_err("%pOF: Could not map the clock registers\n", node);
|
|
return;
|
|
}
|
|
|
|
/* Force the PLL-Audio-1x divider to 4 */
|
|
val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
|
|
val &= ~GENMASK(19, 16);
|
|
writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
|
|
|
|
sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc);
|
|
}
|
|
CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
|
|
sun8i_v3s_ccu_setup);
|