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c00701125c
is_trbe_available() checks for the TRBE support via extracting TraceBuffer field value from ID_AA64DFR0_EL1, and ensures that it is implemented. This replaces the open encoding '0b0001' with 'ID_AA64DFR0_EL1_TraceBuffer_IMP' which is now available via sysreg tools. Functional change is not intended. Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: James Clark <james.clark@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: James Clark <james.clark@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230802063658.1069813-1-anshuman.khandual@arm.com
138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This contains all required hardware related helper functions for
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* Trace Buffer Extension (TRBE) driver in the coresight framework.
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*
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* Copyright (C) 2020 ARM Ltd.
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*
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* Author: Anshuman Khandual <anshuman.khandual@arm.com>
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*/
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#include <linux/coresight.h>
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#include <linux/device.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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#include "coresight-etm-perf.h"
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static inline bool is_trbe_available(void)
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{
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u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
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unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0,
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ID_AA64DFR0_EL1_TraceBuffer_SHIFT);
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return trbe >= ID_AA64DFR0_EL1_TraceBuffer_IMP;
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}
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static inline bool is_trbe_enabled(void)
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{
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u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
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return trblimitr & TRBLIMITR_EL1_E;
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}
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#define TRBE_EC_OTHERS 0
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#define TRBE_EC_STAGE1_ABORT 36
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#define TRBE_EC_STAGE2_ABORT 37
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static inline int get_trbe_ec(u64 trbsr)
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{
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return (trbsr & TRBSR_EL1_EC_MASK) >> TRBSR_EL1_EC_SHIFT;
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}
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#define TRBE_BSC_NOT_STOPPED 0
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#define TRBE_BSC_FILLED 1
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#define TRBE_BSC_TRIGGERED 2
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static inline int get_trbe_bsc(u64 trbsr)
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{
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return (trbsr & TRBSR_EL1_BSC_MASK) >> TRBSR_EL1_BSC_SHIFT;
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}
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static inline void clr_trbe_irq(void)
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{
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u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
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trbsr &= ~TRBSR_EL1_IRQ;
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write_sysreg_s(trbsr, SYS_TRBSR_EL1);
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}
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static inline bool is_trbe_irq(u64 trbsr)
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{
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return trbsr & TRBSR_EL1_IRQ;
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}
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static inline bool is_trbe_trg(u64 trbsr)
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{
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return trbsr & TRBSR_EL1_TRG;
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}
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static inline bool is_trbe_wrap(u64 trbsr)
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{
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return trbsr & TRBSR_EL1_WRAP;
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}
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static inline bool is_trbe_abort(u64 trbsr)
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{
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return trbsr & TRBSR_EL1_EA;
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}
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static inline bool is_trbe_running(u64 trbsr)
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{
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return !(trbsr & TRBSR_EL1_S);
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}
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static inline bool get_trbe_flag_update(u64 trbidr)
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{
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return trbidr & TRBIDR_EL1_F;
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}
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static inline bool is_trbe_programmable(u64 trbidr)
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{
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return !(trbidr & TRBIDR_EL1_P);
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}
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static inline int get_trbe_address_align(u64 trbidr)
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{
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return (trbidr & TRBIDR_EL1_Align_MASK) >> TRBIDR_EL1_Align_SHIFT;
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}
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static inline unsigned long get_trbe_write_pointer(void)
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{
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return read_sysreg_s(SYS_TRBPTR_EL1);
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}
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static inline void set_trbe_write_pointer(unsigned long addr)
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{
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WARN_ON(is_trbe_enabled());
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write_sysreg_s(addr, SYS_TRBPTR_EL1);
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}
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static inline unsigned long get_trbe_limit_pointer(void)
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{
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u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
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unsigned long addr = trblimitr & TRBLIMITR_EL1_LIMIT_MASK;
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WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
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return addr;
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}
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static inline unsigned long get_trbe_base_pointer(void)
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{
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u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
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unsigned long addr = trbbaser & TRBBASER_EL1_BASE_MASK;
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WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
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return addr;
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}
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static inline void set_trbe_base_pointer(unsigned long addr)
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{
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WARN_ON(is_trbe_enabled());
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WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_EL1_BASE_SHIFT)));
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WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
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write_sysreg_s(addr, SYS_TRBBASER_EL1);
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}
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