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c5f94ae639
Exciting functionality is on the way to this device. But before we can add it, we need to do some basic housekeeping so the additions can be added cleanly. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
417 lines
10 KiB
C
417 lines
10 KiB
C
/*
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* PWM device driver for ST SoCs.
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* Author: Ajit Pal Singh <ajitpal.singh@st.com>
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*
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* Copyright (C) 2013-2014 STMicroelectronics (R&D) Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/math64.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
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#define STI_PWM_CTRL 0x50 /* Control/Config register */
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#define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
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#define PWM_PRESCALE_LOW_MASK 0x0f
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#define PWM_PRESCALE_HIGH_MASK 0xf0
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/* Regfield IDs */
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enum {
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/* Bits in PWM_CTRL*/
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PWMCLK_PRESCALE_LOW,
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PWMCLK_PRESCALE_HIGH,
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PWM_OUT_EN,
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PWM_CPT_INT_EN,
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/* Keep last */
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MAX_REGFIELDS
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};
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struct sti_pwm_compat_data {
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const struct reg_field *reg_fields;
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unsigned int num_devs;
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unsigned int max_pwm_cnt;
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unsigned int max_prescale;
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};
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struct sti_pwm_chip {
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struct device *dev;
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unsigned long clk_rate;
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struct clk *pwm_clk;
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struct regmap *regmap;
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struct sti_pwm_compat_data *cdata;
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struct regmap_field *prescale_low;
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struct regmap_field *prescale_high;
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struct regmap_field *pwm_out_en;
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struct regmap_field *pwm_cpt_int_en;
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struct pwm_chip chip;
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struct pwm_device *cur;
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unsigned long configured;
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unsigned int en_count;
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struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
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void __iomem *mmio;
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};
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static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
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[PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
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[PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
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[PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
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[PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
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};
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static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
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{
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return container_of(chip, struct sti_pwm_chip, chip);
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}
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/*
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* Calculate the prescaler value corresponding to the period.
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*/
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static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
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unsigned int *prescale)
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{
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struct sti_pwm_compat_data *cdata = pc->cdata;
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unsigned long val;
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unsigned int ps;
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/*
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* prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_count + 1)) - 1
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*/
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val = NSEC_PER_SEC / pc->clk_rate;
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val *= cdata->max_pwm_cnt + 1;
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if (period % val) {
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return -EINVAL;
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} else {
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ps = period / val - 1;
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if (ps > cdata->max_prescale)
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return -EINVAL;
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}
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*prescale = ps;
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return 0;
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}
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/*
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* For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles.
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* The only way to change the period (apart from changing the PWM input clock)
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* is to change the PWM clock prescaler.
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* The prescaler is of 8 bits, so 256 prescaler values and hence
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* 256 possible period values are supported (for a particular clock rate).
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* The requested period will be applied only if it matches one of these
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* 256 values.
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*/
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static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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struct sti_pwm_compat_data *cdata = pc->cdata;
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struct pwm_device *cur = pc->cur;
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struct device *dev = pc->dev;
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unsigned int prescale = 0, pwmvalx;
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int ret;
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unsigned int ncfg;
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bool period_same = false;
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ncfg = hweight_long(pc->configured);
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if (ncfg)
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period_same = (period_ns == pwm_get_period(cur));
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/* Allow configuration changes if one of the
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* following conditions satisfy.
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* 1. No devices have been configured.
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* 2. Only one device has been configured and the new request
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* is for the same device.
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* 3. Only one device has been configured and the new request is
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* for a new device and period of the new device is same as
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* the current configured period.
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* 4. More than one devices are configured and period of the new
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* requestis the same as the current period.
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*/
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if (!ncfg ||
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((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
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((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
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((ncfg > 1) && period_same)) {
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/* Enable clock before writing to PWM registers. */
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ret = clk_enable(pc->pwm_clk);
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if (ret)
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return ret;
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if (!period_same) {
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ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
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if (ret)
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goto clk_dis;
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ret =
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regmap_field_write(pc->prescale_low,
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prescale & PWM_PRESCALE_LOW_MASK);
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if (ret)
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goto clk_dis;
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ret =
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regmap_field_write(pc->prescale_high,
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(prescale & PWM_PRESCALE_HIGH_MASK) >> 4);
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if (ret)
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goto clk_dis;
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}
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/*
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* When PWMVal == 0, PWM pulse = 1 local clock cycle.
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* When PWMVal == max_pwm_count,
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* PWM pulse = (max_pwm_count + 1) local cycles,
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* that is continuous pulse: signal never goes low.
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*/
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pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns;
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ret = regmap_write(pc->regmap,
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PWM_OUT_VAL(pwm->hwpwm), pwmvalx);
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if (ret)
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goto clk_dis;
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ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
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set_bit(pwm->hwpwm, &pc->configured);
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pc->cur = pwm;
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dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n",
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prescale, period_ns, duty_ns, pwmvalx);
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} else {
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return -EINVAL;
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}
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clk_dis:
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clk_disable(pc->pwm_clk);
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return ret;
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}
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static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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struct device *dev = pc->dev;
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int ret = 0;
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/*
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* Since we have a common enable for all PWM devices,
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* do not enable if already enabled.
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*/
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mutex_lock(&pc->sti_pwm_lock);
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if (!pc->en_count) {
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ret = clk_enable(pc->pwm_clk);
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if (ret)
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goto out;
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ret = regmap_field_write(pc->pwm_out_en, 1);
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if (ret) {
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dev_err(dev, "failed to enable PWM device:%d\n",
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pwm->hwpwm);
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goto out;
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}
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}
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pc->en_count++;
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out:
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mutex_unlock(&pc->sti_pwm_lock);
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return ret;
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}
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static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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mutex_lock(&pc->sti_pwm_lock);
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if (--pc->en_count) {
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mutex_unlock(&pc->sti_pwm_lock);
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return;
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}
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regmap_field_write(pc->pwm_out_en, 0);
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clk_disable(pc->pwm_clk);
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mutex_unlock(&pc->sti_pwm_lock);
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}
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static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
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clear_bit(pwm->hwpwm, &pc->configured);
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}
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static const struct pwm_ops sti_pwm_ops = {
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.config = sti_pwm_config,
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.enable = sti_pwm_enable,
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.disable = sti_pwm_disable,
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.free = sti_pwm_free,
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.owner = THIS_MODULE,
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};
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static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
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{
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struct device *dev = pc->dev;
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const struct reg_field *reg_fields;
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struct device_node *np = dev->of_node;
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struct sti_pwm_compat_data *cdata = pc->cdata;
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u32 num_devs;
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of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
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if (num_devs)
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cdata->num_devs = num_devs;
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reg_fields = cdata->reg_fields;
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pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWMCLK_PRESCALE_LOW]);
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if (IS_ERR(pc->prescale_low))
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return PTR_ERR(pc->prescale_low);
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pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWMCLK_PRESCALE_HIGH]);
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if (IS_ERR(pc->prescale_high))
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return PTR_ERR(pc->prescale_high);
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pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWM_OUT_EN]);
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if (IS_ERR(pc->pwm_out_en))
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return PTR_ERR(pc->pwm_out_en);
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pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
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reg_fields[PWM_CPT_INT_EN]);
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if (IS_ERR(pc->pwm_cpt_int_en))
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return PTR_ERR(pc->pwm_cpt_int_en);
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return 0;
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}
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static const struct regmap_config sti_pwm_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int sti_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sti_pwm_compat_data *cdata;
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struct sti_pwm_chip *pc;
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struct resource *res;
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int ret;
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pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
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if (!cdata)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pc->mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(pc->mmio))
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return PTR_ERR(pc->mmio);
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pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
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&sti_pwm_regmap_config);
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if (IS_ERR(pc->regmap))
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return PTR_ERR(pc->regmap);
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/*
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* Setup PWM data with default values: some values could be replaced
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* with specific ones provided from Device Tree.
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*/
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cdata->reg_fields = &sti_pwm_regfields[0];
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cdata->max_prescale = 0xff;
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cdata->max_pwm_cnt = 255;
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cdata->num_devs = 1;
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pc->cdata = cdata;
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pc->dev = dev;
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pc->en_count = 0;
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mutex_init(&pc->sti_pwm_lock);
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ret = sti_pwm_probe_dt(pc);
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if (ret)
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return ret;
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pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
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if (IS_ERR(pc->pwm_clk)) {
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dev_err(dev, "failed to get PWM clock\n");
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return PTR_ERR(pc->pwm_clk);
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}
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pc->clk_rate = clk_get_rate(pc->pwm_clk);
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if (!pc->clk_rate) {
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dev_err(dev, "failed to get clock rate\n");
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return -EINVAL;
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}
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ret = clk_prepare(pc->pwm_clk);
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if (ret) {
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dev_err(dev, "failed to prepare clock\n");
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return ret;
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}
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pc->chip.dev = dev;
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pc->chip.ops = &sti_pwm_ops;
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pc->chip.base = -1;
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pc->chip.npwm = pc->cdata->num_devs;
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pc->chip.can_sleep = true;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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clk_unprepare(pc->pwm_clk);
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return ret;
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}
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platform_set_drvdata(pdev, pc);
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return 0;
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}
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static int sti_pwm_remove(struct platform_device *pdev)
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{
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struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
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unsigned int i;
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for (i = 0; i < pc->cdata->num_devs; i++)
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pwm_disable(&pc->chip.pwms[i]);
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clk_unprepare(pc->pwm_clk);
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return pwmchip_remove(&pc->chip);
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}
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static const struct of_device_id sti_pwm_of_match[] = {
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{ .compatible = "st,sti-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
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static struct platform_driver sti_pwm_driver = {
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.driver = {
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.name = "sti-pwm",
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.of_match_table = sti_pwm_of_match,
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},
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.probe = sti_pwm_probe,
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.remove = sti_pwm_remove,
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};
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module_platform_driver(sti_pwm_driver);
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MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
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MODULE_LICENSE("GPL");
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