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c7e73b5051
Remove board specific PHY fixup introduced by commit:
| 709bc0657fe6f9f5 ("ARM: imx6ul: add fec MAC refrence clock and phy fixup init")
This fixup addresses boards with a specific configuration: a KSZ8081RNA
PHY with attached clock source to XI (Pin 8) of the PHY equal to 50MHz.
For the KSZ8081RND PHY, the meaning of the reg 0x1F bit 7 is different
(compared to the KSZ8081RNA). A set bit means:
- KSZ8081RNA: clock input to XI (Pin 8) is 50MHz for RMII
- KSZ8081RND: clock input to XI (Pin 8) is 25MHz for RMII
In other configurations, for example a KSZ8081RND PHY or a KSZ8081RNA
with 25Mhz clock source, the PHY will glitch and stay in not recoverable
state.
It is not possible to detect the clock source frequency of the PHY. And
it is not possible to automatically detect KSZ8081 PHY variant - both
have same PHY ID. It is not possible to overwrite the fixup
configuration by providing proper device tree description. The only way
is to remove this fixup.
If this patch breaks network functionality on your board, fix it by
adding PHY node with following properties:
ethernet-phy@x {
...
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
...
};
The board which was referred in the initial patch is already fixed.
See: arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/micrel_phy.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "cpuidle.h"
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static void __init imx6ul_enet_clk_init(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
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if (!IS_ERR(gpr))
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
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IMX6UL_GPR1_ENET_CLK_OUTPUT);
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else
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pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
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}
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static inline void imx6ul_enet_init(void)
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{
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imx6ul_enet_clk_init();
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}
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static void __init imx6ul_init_machine(void)
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{
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of_platform_default_populate(NULL, NULL, NULL);
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imx6ul_enet_init();
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imx_anatop_init();
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imx6ul_pm_init();
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}
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static void __init imx6ul_init_irq(void)
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{
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imx_init_revision_from_anatop();
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imx_src_init();
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irqchip_init();
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imx6_pm_ccm_init("fsl,imx6ul-ccm");
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}
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static void __init imx6ul_init_late(void)
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{
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imx6sx_cpuidle_init();
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
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platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
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}
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static const char * const imx6ul_dt_compat[] __initconst = {
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"fsl,imx6ul",
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"fsl,imx6ull",
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NULL,
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};
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DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
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.init_irq = imx6ul_init_irq,
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.init_machine = imx6ul_init_machine,
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.init_late = imx6ul_init_late,
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.dt_compat = imx6ul_dt_compat,
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MACHINE_END
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