Palmer Dabbelt c901e45a99 RISC-V: sfence.vma orderes the instruction cache ...

This is just a comment change, but it's one that bit me on the mailing
list.  It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering.  This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.

CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2017-11-28 14:06:17 -08:00

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RISC-V: sfence.vma orderes the instruction cache

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