Linus Torvalds 91dbbe6c9f RISC-V Paches for the 6.13 Merge Window, Part 1 ... * Support for pointer masking in userspace, * Support for probing vector misaligned access performance. * Support for qspinlock on systems with Zacas and Zabha. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmdHNu4THHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiZW7D/oCjSIdBHZ6OJN8vATRn2FoHedMgKzE 8OF0EXX85+PNmznxzyUirPerfQPcog5422vCKLUR5h8QD0x3wdMH8gUaV0Wa11k8 ldXlV903k7gJLtJMnww2Eiha7kds5XpNWsWBTU0sBAxt2mMUE2VlloBY5YM/fitJ 3TUihA7vyic5J0H3H4VrkuEoFnN4Xl9WclbwCYFg0uKmiogqXCe5LKey5/JjLpDR 2DdFe/7PRjQMuUNVrNO4Vm+/YD1nwRdg5ukvIl42KINHWKyn1hl23cKsFobrilw5 GyMbTzP4hBhy3kpX+zjWPpvTyoHSww7iJK6AvkvgQk/gua8M6abLJheachY/Ciz1 lJy4okB8H2LtZwMYlJiIXBQzKE1qCwNA1/m24y8SUYQXvjxwGZxaPXAyWvvqBxOP /q/jQYfCiQi/h7BncMv9F8cxkU3J8cglzmxTKlM5Rf5YKdOzMyf4t0sm2pPsFX2l V4xjZQNMDJ1IHGnRbeMTOqHN6iKymyj8BKph5kATO5W9gq4tWXRSEIPfuGJMq2jq T64RweOdHlBPhiXu4hMmRXgT2rNBfTuaqEsVgXAZWkPmqum9uDPjBBiJ89bQO6pk dJl7jVJ27HKSd4zLwnxSGCsVahirF4CCtULRam08500Gfz6dEarD7shZznd86cEg QiBXqK5W6IWyJw== =ND+J -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-v updates from Palmer Dabbelt: - Support for pointer masking in userspace - Support for probing vector misaligned access performance - Support for qspinlock on systems with Zacas and Zabha * tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits) RISC-V: Remove unnecessary include from compat.h riscv: Fix default misaligned access trap riscv: Add qspinlock support dt-bindings: riscv: Add Ziccrse ISA extension description riscv: Add ISA extension parsing for Ziccrse asm-generic: ticket-lock: Add separate ticket-lock.h asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock riscv: Implement xchg8/16() using Zabha riscv: Implement arch_cmpxchg128() using Zacas riscv: Improve zacas fully-ordered cmpxchg() riscv: Implement cmpxchg8/16() using Zabha dt-bindings: riscv: Add Zabha ISA extension description riscv: Implement cmpxchg32/64() using Zacas riscv: Do not fail to build on byte/halfword operations with Zawrs riscv: Move cpufeature.h macros into their own header KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests riscv: hwprobe: Export the Supm ISA extension riscv: selftests: Add a pointer masking test riscv: Allow ptrace control of the tagged address ABI ...		2024-11-27 11:19:09 -08:00
..
.gitignore	RISC-V: Fix the VDSO symbol generaton for binutils-2.35+	2020-11-06 00:03:48 -08:00
flush_icache.S	riscv: Use SYM_*() assembly macros instead of deprecated ones	2023-11-06 09:42:47 -08:00
gen_vdso_offsets.sh	riscv: explicitly use symbol offsets for VDSO	2021-08-24 21:45:47 -07:00
getcpu.S	riscv: Use SYM_*() assembly macros instead of deprecated ones	2023-11-06 09:42:47 -08:00
hwprobe.c	vdso: Rename struct arch_vdso_data to arch_vdso_time_data	2024-11-02 12:37:36 +01:00
Makefile	riscv: Check that vdso does not contain any dynamic relocations	2024-10-24 10:52:53 -07:00
note.S	riscv: add Linux note to vdso	2020-05-04 14:22:34 -07:00
rt_sigreturn.S	riscv: Use SYM_*() assembly macros instead of deprecated ones	2023-11-06 09:42:47 -08:00
sys_hwprobe.S	riscv: Use SYM_*() assembly macros instead of deprecated ones	2023-11-06 09:42:47 -08:00
vdso.lds.S	riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr	2023-11-05 14:15:14 -08:00
vdso.S	riscv: compat: vdso: Add COMPAT_VDSO base code implementation	2022-04-26 13:36:53 -07:00
vgettimeofday.c	arch: vdso: consolidate gettime prototypes	2023-11-23 11:32:32 +01:00