Emil Renner Berthing 0d5701dc9c soc: sifive: ccache: Add StarFive JH7100 support ...

This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.

The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
exension, so instead we need to use this cache controller for
non-standard cache management operations.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

2023-11-22 11:58:14 +00:00

..

ax45mp_cache.c

cache: Add L2 cache management for Andes AX45MP RISC-V core

2023-09-01 09:08:59 -07:00

Kconfig

soc: sifive: shunt ccache driver to drivers/cache

2023-11-22 11:49:25 +00:00

Makefile

soc: sifive: shunt ccache driver to drivers/cache

2023-11-22 11:49:25 +00:00

sifive_ccache.c

soc: sifive: ccache: Add StarFive JH7100 support

2023-11-22 11:58:14 +00:00