Stephen Boyd 8defec031c Fixes for a wrong clockname, a wrong clock-parent, a wrong clock-gate
and finally one new PLL rate for the rk3568 to fix display artifacts
 on a handheld devices based on that soc.
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Merge tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

Pull Rockchip clk driver fixes for the merge window from Heiko Stuebner:

Fixes for a wrong clockname, a wrong clock-parent, a wrong clock-gate
and finally one new PLL rate for the rk3568 to fix display artifacts
on a handheld devices based on that soc.

* tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
  clk: rockchip: rk3128: Fix aclk_peri_src's parent
  clk: rockchip: rk3128: Fix HCLK_OTG gate register
  clk: rockchip: rk3568: Add PLL rate for 292.5MHz
2023-12-13 15:26:24 -08:00
..
2022-03-11 18:22:15 -08:00
2023-10-23 20:16:21 -07:00
2022-10-03 12:34:32 -07:00
2023-06-29 15:28:33 -07:00
2023-10-23 20:16:21 -07:00