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4039213737
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs, as listed in Table 8.3 ("Clock List")
of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
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#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R9A07G044 CPG Core Clocks */
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#define R9A07G044_CLK_I 0
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#define R9A07G044_CLK_I2 1
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#define R9A07G044_CLK_G 2
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#define R9A07G044_CLK_S0 3
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#define R9A07G044_CLK_S1 4
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#define R9A07G044_CLK_SPI0 5
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#define R9A07G044_CLK_SPI1 6
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#define R9A07G044_CLK_SD0 7
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#define R9A07G044_CLK_SD1 8
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#define R9A07G044_CLK_M0 9
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#define R9A07G044_CLK_M1 10
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#define R9A07G044_CLK_M2 11
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#define R9A07G044_CLK_M3 12
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#define R9A07G044_CLK_M4 13
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#define R9A07G044_CLK_HP 14
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#define R9A07G044_CLK_TSU 15
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#define R9A07G044_CLK_ZT 16
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#define R9A07G044_CLK_P0 17
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#define R9A07G044_CLK_P1 18
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#define R9A07G044_CLK_P2 19
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#define R9A07G044_CLK_AT 20
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#define R9A07G044_OSCCLK 21
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/* R9A07G044 Module Clocks */
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#define R9A07G044_CLK_GIC600 0
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#define R9A07G044_CLK_IA55 1
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#define R9A07G044_CLK_SYC 2
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#define R9A07G044_CLK_DMAC 3
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#define R9A07G044_CLK_SYSC 4
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#define R9A07G044_CLK_MTU 5
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#define R9A07G044_CLK_GPT 6
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#define R9A07G044_CLK_ETH0 7
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#define R9A07G044_CLK_ETH1 8
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#define R9A07G044_CLK_I2C0 9
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#define R9A07G044_CLK_I2C1 10
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#define R9A07G044_CLK_I2C2 11
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#define R9A07G044_CLK_I2C3 12
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#define R9A07G044_CLK_SCIF0 13
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#define R9A07G044_CLK_SCIF1 14
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#define R9A07G044_CLK_SCIF2 15
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#define R9A07G044_CLK_SCIF3 16
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#define R9A07G044_CLK_SCIF4 17
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#define R9A07G044_CLK_SCI0 18
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#define R9A07G044_CLK_SCI1 19
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#define R9A07G044_CLK_GPIO 20
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#define R9A07G044_CLK_SDHI0 21
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#define R9A07G044_CLK_SDHI1 22
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#define R9A07G044_CLK_USB0 23
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#define R9A07G044_CLK_USB1 24
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#define R9A07G044_CLK_CANFD 25
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#define R9A07G044_CLK_SSI0 26
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#define R9A07G044_CLK_SSI1 27
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#define R9A07G044_CLK_SSI2 28
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#define R9A07G044_CLK_SSI3 29
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#define R9A07G044_CLK_MHU 30
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#define R9A07G044_CLK_OSTM0 31
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#define R9A07G044_CLK_OSTM1 32
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#define R9A07G044_CLK_OSTM2 33
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#define R9A07G044_CLK_WDT0 34
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#define R9A07G044_CLK_WDT1 35
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#define R9A07G044_CLK_WDT2 36
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#define R9A07G044_CLK_WDT_PON 37
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#define R9A07G044_CLK_GPU 38
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#define R9A07G044_CLK_ISU 39
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#define R9A07G044_CLK_H264 40
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#define R9A07G044_CLK_CRU 41
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#define R9A07G044_CLK_MIPI_DSI 42
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#define R9A07G044_CLK_LCDC 43
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#define R9A07G044_CLK_SRC 44
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#define R9A07G044_CLK_RSPI0 45
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#define R9A07G044_CLK_RSPI1 46
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#define R9A07G044_CLK_RSPI2 47
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#define R9A07G044_CLK_ADC 48
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#define R9A07G044_CLK_TSU_PCLK 49
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#define R9A07G044_CLK_SPI 50
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#define R9A07G044_CLK_MIPI_DSI_V 51
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#define R9A07G044_CLK_MIPI_DSI_PIN 52
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#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
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