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efeeaefe9b
Introduces a driver for the LogiCVC display controller, a programmable logic controller optimized for use in Xilinx Zynq-7000 SoCs and other Xilinx FPGAs. The controller is mostly configured at logic synthesis time so only a subset of configuration is left for the driver to handle. The following features are implemented and tested: - LVDS 4-bit interface; - RGB565 pixel formats; - Multiple layers and hardware composition; - Layer-wide alpha mode; The following features are implemented but untested: - Other RGB pixel formats; - Layer framebuffer configuration for version 4; - Lowest-layer used as background color; - Per-pixel alpha mode. The following features are not implemented: - YUV pixel formats; - DVI, LVDS 3-bit, ITU656 and camera link interfaces; - External parallel input for layer; - Color-keying; - LUT-based alpha modes. Additional implementation-specific notes: - Panels are only enabled after the first page flip to avoid flashing a white screen. - Depth used in context of the LogiCVC driver only counts color components to match the definition of the synthesis parameters. Support is implemented for both version 3 and 4 of the controller. With version 3, framebuffers are stored in a dedicated contiguous memory area, with a base address hardcoded for each layer. This requires using a dedicated CMA pool registered at the base address and tweaking a few offset-related registers to try to use any buffer allocated from the pool. This is done on a best-effort basis to have the hardware cope with the DRM framebuffer allocation model and there is no guarantee that each buffer allocated by GEM CMA can be used for any layer. In particular, buffers allocated below the base address for a layer are guaranteed not to be configurable for that layer. See the implementation of logicvc_layer_buffer_find_setup for specifics. Version 4 allows configuring each buffer address directly, which guarantees that any buffer can be configured. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220520141555.1429041-2-paul.kocialkowski@bootlin.com
68 lines
1.5 KiB
C
68 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2022 Bootlin
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* Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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*/
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#ifndef _LOGICVC_DRM_H_
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#define _LOGICVC_DRM_H_
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <drm/drm_device.h>
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#define LOGICVC_DISPLAY_INTERFACE_RGB 0
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#define LOGICVC_DISPLAY_INTERFACE_ITU656 1
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#define LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS 2
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#define LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS_CAMERA 3
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#define LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS 4
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#define LOGICVC_DISPLAY_INTERFACE_DVI 5
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#define LOGICVC_DISPLAY_COLORSPACE_RGB 0
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#define LOGICVC_DISPLAY_COLORSPACE_YUV422 1
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#define LOGICVC_DISPLAY_COLORSPACE_YUV444 2
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#define logicvc_drm(d) \
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container_of(d, struct logicvc_drm, drm_dev)
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struct logicvc_crtc;
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struct logicvc_interface;
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struct logicvc_drm_config {
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u32 display_interface;
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u32 display_colorspace;
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u32 display_depth;
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u32 row_stride;
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bool dithering;
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bool background_layer;
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bool layers_configurable;
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u32 layers_count;
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};
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struct logicvc_drm_caps {
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unsigned int major;
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unsigned int minor;
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char level;
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bool layer_address;
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};
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struct logicvc_drm {
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const struct logicvc_drm_caps *caps;
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struct logicvc_drm_config config;
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struct drm_device drm_dev;
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phys_addr_t reserved_mem_base;
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struct regmap *regmap;
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struct clk *vclk;
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struct clk *vclk2;
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struct clk *lvdsclk;
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struct clk *lvdsclkn;
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struct list_head layers_list;
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struct logicvc_crtc *crtc;
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struct logicvc_interface *interface;
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};
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#endif
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