linux/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 *
 * Copyright (C) 2024 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__

#define VBATTB_XC		0
#define VBATTB_XBYP		1
#define VBATTB_MUX		2
#define VBATTB_VBATTCLK		3

#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */
dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->\| \|----->\| \ +----+ VBATTCLK \| 32K clock\| \| \|----->\|gate\|-----------> \| osc \| XBYP \| \| +----+ RTXOUT --->\| \|----->\| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2024-11-01 11:57:12 +02:00			`/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)`
			`*`
			`* Copyright (C) 2024 Renesas Electronics Corp.`
			`*/`
			`#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__`
			`#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__`

			`#define VBATTB_XC 0`
			`#define VBATTB_XBYP 1`
			`#define VBATTB_MUX 2`
			`#define VBATTB_VBATTCLK 3`

			`#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */`