2019-05-27 08:55:01 +02:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
2006-11-11 17:24:53 +11:00
|
|
|
/*
|
|
|
|
* "Indirect" DCR access
|
|
|
|
*
|
|
|
|
* Copyright (c) 2004 Eugene Surovegin <ebs@ebshome.net>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <asm/ppc_asm.h>
|
|
|
|
#include <asm/processor.h>
|
2008-12-18 19:13:22 +00:00
|
|
|
#include <asm/bug.h>
|
2016-01-13 23:33:46 -05:00
|
|
|
#include <asm/export.h>
|
2006-11-11 17:24:53 +11:00
|
|
|
|
|
|
|
#define DCR_ACCESS_PROLOG(table) \
|
powerpc/dcr: Use cmplwi instead of 3-argument cmpli
In dcr-low.S we use cmpli with three arguments, instead of four
arguments as defined in the ISA:
cmpli cr0,r3,1024
This appears to be a PPC440-ism, looking at the "PPC440x5 CPU Core
User’s Manual" it shows cmpli having no L field, but implied to be 0 due
to the core being 32-bit. It mentions that the ISA defines four
arguments and recommends using cmplwi.
It also corresponds to the old POWER instruction set, which had no L
field there, a reserved bit instead.
dcr-low.S is only built 32-bit, because it is only built when
DCR_NATIVE=y, which is only selected by 40x and 44x. Looking at the
generated code (with gcc/gas) we see cmplwi as expected.
Although gas is happy with the 3-argument version when building for
32-bit, the LLVM assembler is not and errors out with:
arch/powerpc/sysdev/dcr-low.S:27:10: error: invalid operand for instruction
cmpli 0,%r3,1024; ...
^
Switch to the cmplwi extended opcode, which avoids any confusion when
reading the ISA, fixes the issue with the LLVM assembler, and also means
the code could be built 64-bit in future (though that's very unlikely).
Reported-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
BugLink: https://github.com/ClangBuiltLinux/linux/issues/1419
Link: https://lore.kernel.org/r/20211014024424.528848-1-mpe@ellerman.id.au
2021-10-14 13:44:24 +11:00
|
|
|
cmplwi cr0,r3,1024; \
|
2006-11-11 17:24:53 +11:00
|
|
|
rlwinm r3,r3,4,18,27; \
|
|
|
|
lis r5,table@h; \
|
|
|
|
ori r5,r5,table@l; \
|
|
|
|
add r3,r3,r5; \
|
2008-12-18 19:13:22 +00:00
|
|
|
bge- 1f; \
|
2006-11-11 17:24:53 +11:00
|
|
|
mtctr r3; \
|
2008-12-18 19:13:22 +00:00
|
|
|
bctr; \
|
|
|
|
1: trap; \
|
|
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0; \
|
|
|
|
blr
|
2006-11-11 17:24:53 +11:00
|
|
|
|
|
|
|
_GLOBAL(__mfdcr)
|
|
|
|
DCR_ACCESS_PROLOG(__mfdcr_table)
|
2016-01-13 23:33:46 -05:00
|
|
|
EXPORT_SYMBOL(__mfdcr)
|
2006-11-11 17:24:53 +11:00
|
|
|
|
|
|
|
_GLOBAL(__mtdcr)
|
|
|
|
DCR_ACCESS_PROLOG(__mtdcr_table)
|
2016-01-13 23:33:46 -05:00
|
|
|
EXPORT_SYMBOL(__mtdcr)
|
2006-11-11 17:24:53 +11:00
|
|
|
|
|
|
|
__mfdcr_table:
|
|
|
|
mfdcr r3,0; blr
|
|
|
|
__mtdcr_table:
|
|
|
|
mtdcr 0,r4; blr
|
|
|
|
|
|
|
|
dcr = 1
|
|
|
|
.rept 1023
|
|
|
|
mfdcr r3,dcr; blr
|
|
|
|
mtdcr dcr,r4; blr
|
|
|
|
dcr = dcr + 1
|
|
|
|
.endr
|