2019-12-19 17:28:17 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Thermal sensor driver for Allwinner SOC
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* Copyright (C) 2019 Yangtao Li
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*
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* Based on the work of Icenowy Zheng <icenowy@aosc.io>
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* Based on the work of Ondrej Jirman <megous@megous.com>
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* Based on the work of Josef Gajdusek <atx@atx.name>
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*/
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2020-11-09 11:46:24 +00:00
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#include <linux/bitmap.h>
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2024-10-10 18:06:22 +00:00
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#include <linux/cleanup.h>
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2019-12-19 17:28:17 +00:00
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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2023-07-14 17:50:07 +00:00
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#include <linux/of.h>
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2024-02-19 15:36:37 +00:00
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#include <linux/of_platform.h>
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2019-12-19 17:28:17 +00:00
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/thermal.h>
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2019-12-28 17:19:04 +00:00
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#include "thermal_hwmon.h"
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2019-12-19 17:28:17 +00:00
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#define MAX_SENSOR_NUM 4
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#define FT_TEMP_MASK GENMASK(11, 0)
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#define TEMP_CALIB_MASK GENMASK(11, 0)
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#define CALIBRATE_DEFAULT 0x800
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#define SUN8I_THS_CTRL0 0x00
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#define SUN8I_THS_CTRL2 0x40
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#define SUN8I_THS_IC 0x44
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#define SUN8I_THS_IS 0x48
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#define SUN8I_THS_MFC 0x70
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#define SUN8I_THS_TEMP_CALIB 0x74
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#define SUN8I_THS_TEMP_DATA 0x80
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#define SUN50I_THS_CTRL0 0x00
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#define SUN50I_H6_THS_ENABLE 0x04
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#define SUN50I_H6_THS_PC 0x08
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#define SUN50I_H6_THS_DIC 0x10
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#define SUN50I_H6_THS_DIS 0x20
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#define SUN50I_H6_THS_MFC 0x30
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#define SUN50I_H6_THS_TEMP_CALIB 0xa0
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#define SUN50I_H6_THS_TEMP_DATA 0xc0
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#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x))
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#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
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#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
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2024-02-19 15:36:35 +00:00
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#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
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#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
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2019-12-19 17:28:17 +00:00
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#define SUN50I_THS_FILTER_EN BIT(2)
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#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
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#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
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#define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x)
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struct tsensor {
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struct ths_device *tmdev;
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struct thermal_zone_device *tzd;
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int id;
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};
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struct ths_thermal_chip {
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bool has_mod_clk;
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bool has_bus_clk_reset;
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2024-02-19 15:36:37 +00:00
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bool needs_sram;
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2019-12-19 17:28:17 +00:00
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int sensor_num;
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int offset;
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int scale;
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int ft_deviation;
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int temp_data_base;
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int (*calibrate)(struct ths_device *tmdev,
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u16 *caldata, int callen);
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int (*init)(struct ths_device *tmdev);
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2020-11-09 11:46:24 +00:00
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unsigned long (*irq_ack)(struct ths_device *tmdev);
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2019-12-19 17:28:17 +00:00
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int (*calc_temp)(struct ths_device *tmdev,
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int id, int reg);
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};
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struct ths_device {
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const struct ths_thermal_chip *chip;
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struct device *dev;
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struct regmap *regmap;
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2024-02-19 15:36:37 +00:00
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struct regmap_field *sram_regmap_field;
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2019-12-19 17:28:17 +00:00
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struct reset_control *reset;
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struct clk *bus_clk;
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struct clk *mod_clk;
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struct tsensor sensor[MAX_SENSOR_NUM];
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};
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2024-02-19 15:36:37 +00:00
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/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
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static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
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2019-12-19 17:28:17 +00:00
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/* Temp Unit: millidegree Celsius */
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static int sun8i_ths_calc_temp(struct ths_device *tmdev,
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int id, int reg)
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{
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return tmdev->chip->offset - (reg * tmdev->chip->scale / 10);
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}
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static int sun50i_h5_calc_temp(struct ths_device *tmdev,
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int id, int reg)
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{
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if (reg >= 0x500)
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return -1191 * reg / 10 + 223000;
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else if (!id)
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return -1452 * reg / 10 + 259000;
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else
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return -1590 * reg / 10 + 276000;
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}
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2022-08-04 22:43:24 +00:00
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static int sun8i_ths_get_temp(struct thermal_zone_device *tz, int *temp)
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2019-12-19 17:28:17 +00:00
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{
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2023-03-01 20:14:30 +00:00
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struct tsensor *s = thermal_zone_device_priv(tz);
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2019-12-19 17:28:17 +00:00
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struct ths_device *tmdev = s->tmdev;
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int val = 0;
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regmap_read(tmdev->regmap, tmdev->chip->temp_data_base +
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0x4 * s->id, &val);
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/* ths have no data yet */
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if (!val)
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return -EAGAIN;
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*temp = tmdev->chip->calc_temp(tmdev, s->id, val);
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/*
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* According to the original sdk, there are some platforms(rarely)
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* that add a fixed offset value after calculating the temperature
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* value. We can't simply put it on the formula for calculating the
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* temperature above, because the formula for calculating the
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* temperature above is also used when the sensor is calibrated. If
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* do this, the correct calibration formula is hard to know.
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*/
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*temp += tmdev->chip->ft_deviation;
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return 0;
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}
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2022-08-04 22:43:24 +00:00
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static const struct thermal_zone_device_ops ths_ops = {
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2019-12-19 17:28:17 +00:00
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.get_temp = sun8i_ths_get_temp,
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};
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static const struct regmap_config config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.fast_io = true,
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.max_register = 0xfc,
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};
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2020-11-09 11:46:24 +00:00
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static unsigned long sun8i_h3_irq_ack(struct ths_device *tmdev)
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2019-12-19 17:28:17 +00:00
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{
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2020-11-09 11:46:24 +00:00
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unsigned long irq_bitmap = 0;
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int i, state;
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2019-12-19 17:28:17 +00:00
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regmap_read(tmdev->regmap, SUN8I_THS_IS, &state);
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for (i = 0; i < tmdev->chip->sensor_num; i++) {
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if (state & SUN8I_THS_DATA_IRQ_STS(i)) {
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regmap_write(tmdev->regmap, SUN8I_THS_IS,
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SUN8I_THS_DATA_IRQ_STS(i));
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2020-11-09 11:46:24 +00:00
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bitmap_set(&irq_bitmap, i, 1);
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2019-12-19 17:28:17 +00:00
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}
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}
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2020-11-09 11:46:24 +00:00
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return irq_bitmap;
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2019-12-19 17:28:17 +00:00
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}
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2020-11-09 11:46:24 +00:00
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static unsigned long sun50i_h6_irq_ack(struct ths_device *tmdev)
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2019-12-19 17:28:17 +00:00
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{
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2020-11-09 11:46:24 +00:00
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unsigned long irq_bitmap = 0;
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int i, state;
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2019-12-19 17:28:17 +00:00
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regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state);
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for (i = 0; i < tmdev->chip->sensor_num; i++) {
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if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) {
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regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS,
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SUN50I_H6_THS_DATA_IRQ_STS(i));
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2020-11-09 11:46:24 +00:00
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bitmap_set(&irq_bitmap, i, 1);
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2019-12-19 17:28:17 +00:00
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}
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}
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2020-11-09 11:46:24 +00:00
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return irq_bitmap;
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2019-12-19 17:28:17 +00:00
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}
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static irqreturn_t sun8i_irq_thread(int irq, void *data)
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{
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struct ths_device *tmdev = data;
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2020-11-09 11:46:24 +00:00
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unsigned long irq_bitmap = tmdev->chip->irq_ack(tmdev);
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int i;
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2019-12-19 17:28:17 +00:00
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2020-11-09 11:46:24 +00:00
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for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
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2024-01-23 23:33:07 +00:00
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/* We allow some zones to not register. */
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if (IS_ERR(tmdev->sensor[i].tzd))
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continue;
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2020-11-09 11:46:24 +00:00
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thermal_zone_device_update(tmdev->sensor[i].tzd,
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THERMAL_EVENT_UNSPECIFIED);
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2019-12-19 17:28:17 +00:00
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}
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return IRQ_HANDLED;
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}
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static int sun8i_h3_ths_calibrate(struct ths_device *tmdev,
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u16 *caldata, int callen)
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{
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int i;
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if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num)
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return -EINVAL;
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for (i = 0; i < tmdev->chip->sensor_num; i++) {
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int offset = (i % 2) << 4;
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regmap_update_bits(tmdev->regmap,
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SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)),
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2023-01-23 10:23:19 +00:00
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TEMP_CALIB_MASK << offset,
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2019-12-19 17:28:17 +00:00
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caldata[i] << offset);
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}
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return 0;
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}
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static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
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u16 *caldata, int callen)
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{
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struct device *dev = tmdev->dev;
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int i, ft_temp;
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2024-02-19 15:36:36 +00:00
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if (!caldata[0])
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2019-12-19 17:28:17 +00:00
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return -EINVAL;
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/*
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* efuse layout:
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*
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2024-02-19 15:36:36 +00:00
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* 0 11 16 27 32 43 48 57
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* +----------+-----------+-----------+-----------+
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* | temp | |sensor0| |sensor1| |sensor2| |
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* +----------+-----------+-----------+-----------+
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* ^ ^ ^
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* | | |
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* | | sensor3[11:8]
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* | sensor3[7:4]
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* sensor3[3:0]
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2019-12-19 17:28:17 +00:00
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*
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* The calibration data on the H6 is the ambient temperature and
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* sensor values that are filled during the factory test stage.
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*
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2022-05-21 11:10:46 +00:00
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* The unit of stored FT temperature is 0.1 degree celsius.
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2019-12-19 17:28:17 +00:00
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*
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* We need to calculate a delta between measured and caluclated
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* register values and this will become a calibration offset.
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*/
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ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
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for (i = 0; i < tmdev->chip->sensor_num; i++) {
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2024-02-19 15:36:36 +00:00
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int sensor_reg, sensor_temp, cdata, offset;
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if (i == 3)
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sensor_reg = (caldata[1] >> 12)
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| ((caldata[2] >> 12) << 4)
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| ((caldata[3] >> 12) << 8);
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else
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sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
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sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
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2019-12-19 17:28:17 +00:00
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/*
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* Calibration data is CALIBRATE_DEFAULT - (calculated
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* temperature from sensor reading at factory temperature
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* minus actual factory temperature) * 14.88 (scale from
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* temperature to register values)
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*/
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cdata = CALIBRATE_DEFAULT -
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((sensor_temp - ft_temp) * 10 / tmdev->chip->scale);
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if (cdata & ~TEMP_CALIB_MASK) {
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/*
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* Calibration value more than 12-bit, but calibration
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* register is 12-bit. In this case, ths hardware can
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* still work without calibration, although the data
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* won't be so accurate.
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*/
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dev_warn(dev, "sensor%d is not calibrated.\n", i);
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continue;
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}
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offset = (i % 2) * 16;
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regmap_update_bits(tmdev->regmap,
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SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4),
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2023-01-23 10:23:19 +00:00
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TEMP_CALIB_MASK << offset,
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2019-12-19 17:28:17 +00:00
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cdata << offset);
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}
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return 0;
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}
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static int sun8i_ths_calibrate(struct ths_device *tmdev)
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{
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struct nvmem_cell *calcell;
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struct device *dev = tmdev->dev;
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u16 *caldata;
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size_t callen;
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int ret = 0;
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2023-07-19 00:58:54 +00:00
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calcell = nvmem_cell_get(dev, "calibration");
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2019-12-19 17:28:17 +00:00
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if (IS_ERR(calcell)) {
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if (PTR_ERR(calcell) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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/*
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|
* Even if the external calibration data stored in sid is
|
|
|
|
* not accessible, the THS hardware can still work, although
|
|
|
|
* the data won't be so accurate.
|
|
|
|
*
|
|
|
|
* The default value of calibration register is 0x800 for
|
|
|
|
* every sensor, and the calibration value is usually 0x7xx
|
|
|
|
* or 0x8xx, so they won't be away from the default value
|
|
|
|
* for a lot.
|
|
|
|
*
|
2021-03-05 01:43:48 +00:00
|
|
|
* So here we do not return error if the calibration data is
|
2019-12-19 17:28:17 +00:00
|
|
|
* not available, except the probe needs deferring.
|
|
|
|
*/
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
caldata = nvmem_cell_read(calcell, &callen);
|
|
|
|
if (IS_ERR(caldata)) {
|
|
|
|
ret = PTR_ERR(caldata);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmdev->chip->calibrate(tmdev, caldata, callen);
|
|
|
|
|
|
|
|
kfree(caldata);
|
|
|
|
out:
|
2023-07-19 00:58:54 +00:00
|
|
|
if (!IS_ERR(calcell))
|
|
|
|
nvmem_cell_put(calcell);
|
2019-12-19 17:28:17 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2023-05-14 18:46:05 +00:00
|
|
|
static void sun8i_ths_reset_control_assert(void *data)
|
|
|
|
{
|
|
|
|
reset_control_assert(data);
|
|
|
|
}
|
|
|
|
|
2024-02-19 15:36:37 +00:00
|
|
|
static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
|
|
|
|
{
|
|
|
|
struct platform_device *sram_pdev;
|
|
|
|
struct regmap *regmap = NULL;
|
|
|
|
|
2024-10-10 18:06:22 +00:00
|
|
|
struct device_node *sram_node __free(device_node) =
|
|
|
|
of_parse_phandle(node, "allwinner,sram", 0);
|
2024-02-19 15:36:37 +00:00
|
|
|
if (!sram_node)
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
sram_pdev = of_find_device_by_node(sram_node);
|
|
|
|
if (!sram_pdev) {
|
|
|
|
/* platform device might not be probed yet */
|
2024-10-10 18:06:22 +00:00
|
|
|
return ERR_PTR(-EPROBE_DEFER);
|
2024-02-19 15:36:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* If no regmap is found then the other device driver is at fault */
|
|
|
|
regmap = dev_get_regmap(&sram_pdev->dev, NULL);
|
|
|
|
if (!regmap)
|
|
|
|
regmap = ERR_PTR(-EINVAL);
|
|
|
|
|
|
|
|
platform_device_put(sram_pdev);
|
2024-10-10 18:06:22 +00:00
|
|
|
|
2024-02-19 15:36:37 +00:00
|
|
|
return regmap;
|
|
|
|
}
|
|
|
|
|
2019-12-19 17:28:17 +00:00
|
|
|
static int sun8i_ths_resource_init(struct ths_device *tmdev)
|
|
|
|
{
|
|
|
|
struct device *dev = tmdev->dev;
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
void __iomem *base;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
|
|
|
|
|
|
|
tmdev->regmap = devm_regmap_init_mmio(dev, base, &config);
|
|
|
|
if (IS_ERR(tmdev->regmap))
|
|
|
|
return PTR_ERR(tmdev->regmap);
|
|
|
|
|
|
|
|
if (tmdev->chip->has_bus_clk_reset) {
|
2020-01-12 17:13:18 +00:00
|
|
|
tmdev->reset = devm_reset_control_get(dev, NULL);
|
2019-12-19 17:28:17 +00:00
|
|
|
if (IS_ERR(tmdev->reset))
|
|
|
|
return PTR_ERR(tmdev->reset);
|
|
|
|
|
2023-05-14 18:46:05 +00:00
|
|
|
ret = reset_control_deassert(tmdev->reset);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = devm_add_action_or_reset(dev, sun8i_ths_reset_control_assert,
|
|
|
|
tmdev->reset);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
tmdev->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus");
|
2019-12-19 17:28:17 +00:00
|
|
|
if (IS_ERR(tmdev->bus_clk))
|
|
|
|
return PTR_ERR(tmdev->bus_clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tmdev->chip->has_mod_clk) {
|
2023-05-14 18:46:05 +00:00
|
|
|
tmdev->mod_clk = devm_clk_get_enabled(&pdev->dev, "mod");
|
2019-12-19 17:28:17 +00:00
|
|
|
if (IS_ERR(tmdev->mod_clk))
|
|
|
|
return PTR_ERR(tmdev->mod_clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_set_rate(tmdev->mod_clk, 24000000);
|
|
|
|
if (ret)
|
2023-05-14 18:46:05 +00:00
|
|
|
return ret;
|
2019-12-19 17:28:17 +00:00
|
|
|
|
2024-02-19 15:36:37 +00:00
|
|
|
if (tmdev->chip->needs_sram) {
|
|
|
|
struct regmap *regmap;
|
|
|
|
|
|
|
|
regmap = sun8i_ths_get_sram_regmap(dev->of_node);
|
|
|
|
if (IS_ERR(regmap))
|
|
|
|
return PTR_ERR(regmap);
|
|
|
|
tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
|
|
|
|
regmap,
|
|
|
|
sun8i_ths_sram_reg_field);
|
|
|
|
if (IS_ERR(tmdev->sram_regmap_field))
|
|
|
|
return PTR_ERR(tmdev->sram_regmap_field);
|
|
|
|
}
|
|
|
|
|
2019-12-19 17:28:17 +00:00
|
|
|
ret = sun8i_ths_calibrate(tmdev);
|
|
|
|
if (ret)
|
2023-05-14 18:46:05 +00:00
|
|
|
return ret;
|
2019-12-19 17:28:17 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun8i_h3_thermal_init(struct ths_device *tmdev)
|
|
|
|
{
|
|
|
|
int val;
|
|
|
|
|
|
|
|
/* average over 4 samples */
|
|
|
|
regmap_write(tmdev->regmap, SUN8I_THS_MFC,
|
|
|
|
SUN50I_THS_FILTER_EN |
|
|
|
|
SUN50I_THS_FILTER_TYPE(1));
|
|
|
|
/*
|
|
|
|
* clkin = 24MHz
|
|
|
|
* filter_samples = 4
|
|
|
|
* period = 0.25s
|
|
|
|
*
|
|
|
|
* x = period * clkin / 4096 / filter_samples - 1
|
|
|
|
* = 365
|
|
|
|
*/
|
|
|
|
val = GENMASK(7 + tmdev->chip->sensor_num, 8);
|
|
|
|
regmap_write(tmdev->regmap, SUN8I_THS_IC,
|
|
|
|
SUN50I_H6_THS_PC_TEMP_PERIOD(365) | val);
|
|
|
|
/*
|
|
|
|
* T_acq = 20us
|
|
|
|
* clkin = 24MHz
|
|
|
|
*
|
|
|
|
* x = T_acq * clkin - 1
|
|
|
|
* = 479
|
|
|
|
*/
|
|
|
|
regmap_write(tmdev->regmap, SUN8I_THS_CTRL0,
|
|
|
|
SUN8I_THS_CTRL0_T_ACQ0(479));
|
|
|
|
val = GENMASK(tmdev->chip->sensor_num - 1, 0);
|
|
|
|
regmap_write(tmdev->regmap, SUN8I_THS_CTRL2,
|
|
|
|
SUN8I_THS_CTRL2_T_ACQ1(479) | val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_h6_thermal_init(struct ths_device *tmdev)
|
|
|
|
{
|
|
|
|
int val;
|
|
|
|
|
2024-02-19 15:36:37 +00:00
|
|
|
/* The H616 needs to have a bit in the SRAM control register cleared. */
|
|
|
|
if (tmdev->sram_regmap_field)
|
|
|
|
regmap_field_write(tmdev->sram_regmap_field, 0);
|
|
|
|
|
2019-12-19 17:28:17 +00:00
|
|
|
/*
|
2024-02-19 15:36:35 +00:00
|
|
|
* The manual recommends an overall sample frequency of 50 KHz (20us,
|
|
|
|
* 480 cycles at 24 MHz), which provides plenty of time for both the
|
|
|
|
* acquisition time (>24 cycles) and the actual conversion time
|
|
|
|
* (>14 cycles).
|
|
|
|
* The lower half of the CTRL register holds the "acquire time", in
|
|
|
|
* clock cycles, which the manual recommends to be 2us:
|
|
|
|
* 24MHz * 2us = 48 cycles.
|
|
|
|
* The high half of THS_CTRL encodes the sample frequency, in clock
|
|
|
|
* cycles: 24MHz * 20us = 480 cycles.
|
|
|
|
* This is explained in the H616 manual, but apparently wrongly
|
|
|
|
* described in the H6 manual, although the BSP code does the same
|
|
|
|
* for both SoCs.
|
2019-12-19 17:28:17 +00:00
|
|
|
*/
|
|
|
|
regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
|
2024-02-19 15:36:35 +00:00
|
|
|
SUN50I_THS_CTRL0_T_ACQ(48) |
|
|
|
|
SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
|
2019-12-19 17:28:17 +00:00
|
|
|
/* average over 4 samples */
|
|
|
|
regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
|
|
|
|
SUN50I_THS_FILTER_EN |
|
|
|
|
SUN50I_THS_FILTER_TYPE(1));
|
|
|
|
/*
|
|
|
|
* clkin = 24MHz
|
|
|
|
* filter_samples = 4
|
|
|
|
* period = 0.25s
|
|
|
|
*
|
|
|
|
* x = period * clkin / 4096 / filter_samples - 1
|
|
|
|
* = 365
|
|
|
|
*/
|
|
|
|
regmap_write(tmdev->regmap, SUN50I_H6_THS_PC,
|
|
|
|
SUN50I_H6_THS_PC_TEMP_PERIOD(365));
|
|
|
|
/* enable sensor */
|
|
|
|
val = GENMASK(tmdev->chip->sensor_num - 1, 0);
|
|
|
|
regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val);
|
|
|
|
/* thermal data interrupt enable */
|
|
|
|
val = GENMASK(tmdev->chip->sensor_num - 1, 0);
|
|
|
|
regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun8i_ths_register(struct ths_device *tmdev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < tmdev->chip->sensor_num; i++) {
|
|
|
|
tmdev->sensor[i].tmdev = tmdev;
|
|
|
|
tmdev->sensor[i].id = i;
|
|
|
|
tmdev->sensor[i].tzd =
|
2022-08-04 22:43:24 +00:00
|
|
|
devm_thermal_of_zone_register(tmdev->dev,
|
|
|
|
i,
|
|
|
|
&tmdev->sensor[i],
|
|
|
|
&ths_ops);
|
2024-01-23 23:33:07 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If an individual zone fails to register for reasons
|
|
|
|
* other than probe deferral (eg, a bad DT) then carry
|
|
|
|
* on, other zones might register successfully.
|
|
|
|
*/
|
|
|
|
if (IS_ERR(tmdev->sensor[i].tzd)) {
|
|
|
|
if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
|
|
|
|
return PTR_ERR(tmdev->sensor[i].tzd);
|
|
|
|
continue;
|
|
|
|
}
|
2019-12-28 17:19:04 +00:00
|
|
|
|
2023-06-20 09:07:23 +00:00
|
|
|
devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd);
|
2019-12-19 17:28:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun8i_ths_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct ths_device *tmdev;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
int ret, irq;
|
|
|
|
|
|
|
|
tmdev = devm_kzalloc(dev, sizeof(*tmdev), GFP_KERNEL);
|
|
|
|
if (!tmdev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
tmdev->dev = dev;
|
|
|
|
tmdev->chip = of_device_get_match_data(&pdev->dev);
|
|
|
|
if (!tmdev->chip)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = sun8i_ths_resource_init(tmdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0)
|
|
|
|
return irq;
|
|
|
|
|
|
|
|
ret = tmdev->chip->init(tmdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sun8i_ths_register(tmdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Avoid entering the interrupt handler, the thermal device is not
|
|
|
|
* registered yet, we deffer the registration of the interrupt to
|
|
|
|
* the end.
|
|
|
|
*/
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, NULL,
|
|
|
|
sun8i_irq_thread,
|
|
|
|
IRQF_ONESHOT, "ths", tmdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct ths_thermal_chip sun8i_a83t_ths = {
|
|
|
|
.sensor_num = 3,
|
|
|
|
.scale = 705,
|
|
|
|
.offset = 191668,
|
|
|
|
.temp_data_base = SUN8I_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun8i_h3_ths_calibrate,
|
|
|
|
.init = sun8i_h3_thermal_init,
|
|
|
|
.irq_ack = sun8i_h3_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ths_thermal_chip sun8i_h3_ths = {
|
|
|
|
.sensor_num = 1,
|
|
|
|
.scale = 1211,
|
|
|
|
.offset = 217000,
|
|
|
|
.has_mod_clk = true,
|
|
|
|
.has_bus_clk_reset = true,
|
|
|
|
.temp_data_base = SUN8I_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun8i_h3_ths_calibrate,
|
|
|
|
.init = sun8i_h3_thermal_init,
|
|
|
|
.irq_ack = sun8i_h3_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ths_thermal_chip sun8i_r40_ths = {
|
2020-01-06 17:46:38 +00:00
|
|
|
.sensor_num = 2,
|
2019-12-19 17:28:17 +00:00
|
|
|
.offset = 251086,
|
|
|
|
.scale = 1130,
|
|
|
|
.has_mod_clk = true,
|
|
|
|
.has_bus_clk_reset = true,
|
|
|
|
.temp_data_base = SUN8I_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun8i_h3_ths_calibrate,
|
|
|
|
.init = sun8i_h3_thermal_init,
|
|
|
|
.irq_ack = sun8i_h3_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ths_thermal_chip sun50i_a64_ths = {
|
|
|
|
.sensor_num = 3,
|
|
|
|
.offset = 260890,
|
|
|
|
.scale = 1170,
|
|
|
|
.has_mod_clk = true,
|
|
|
|
.has_bus_clk_reset = true,
|
|
|
|
.temp_data_base = SUN8I_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun8i_h3_ths_calibrate,
|
|
|
|
.init = sun8i_h3_thermal_init,
|
|
|
|
.irq_ack = sun8i_h3_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
2020-07-24 07:11:43 +00:00
|
|
|
static const struct ths_thermal_chip sun50i_a100_ths = {
|
|
|
|
.sensor_num = 3,
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.has_bus_clk_reset = true,
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.ft_deviation = 8000,
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.offset = 187744,
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.scale = 672,
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.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
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|
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.calibrate = sun50i_h6_ths_calibrate,
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.init = sun50i_h6_thermal_init,
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.irq_ack = sun50i_h6_irq_ack,
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.calc_temp = sun8i_ths_calc_temp,
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|
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};
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|
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2019-12-19 17:28:17 +00:00
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static const struct ths_thermal_chip sun50i_h5_ths = {
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.sensor_num = 2,
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|
|
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.has_mod_clk = true,
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.has_bus_clk_reset = true,
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|
|
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.temp_data_base = SUN8I_THS_TEMP_DATA,
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|
|
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.calibrate = sun8i_h3_ths_calibrate,
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|
|
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.init = sun8i_h3_thermal_init,
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|
|
|
.irq_ack = sun8i_h3_irq_ack,
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|
|
|
.calc_temp = sun50i_h5_calc_temp,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ths_thermal_chip sun50i_h6_ths = {
|
|
|
|
.sensor_num = 2,
|
|
|
|
.has_bus_clk_reset = true,
|
|
|
|
.ft_deviation = 7000,
|
|
|
|
.offset = 187744,
|
|
|
|
.scale = 672,
|
|
|
|
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun50i_h6_ths_calibrate,
|
|
|
|
.init = sun50i_h6_thermal_init,
|
|
|
|
.irq_ack = sun50i_h6_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
2023-12-17 21:06:23 +00:00
|
|
|
static const struct ths_thermal_chip sun20i_d1_ths = {
|
|
|
|
.sensor_num = 1,
|
|
|
|
.has_bus_clk_reset = true,
|
|
|
|
.offset = 188552,
|
|
|
|
.scale = 673,
|
|
|
|
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun50i_h6_ths_calibrate,
|
|
|
|
.init = sun50i_h6_thermal_init,
|
|
|
|
.irq_ack = sun50i_h6_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
2024-02-19 15:36:38 +00:00
|
|
|
static const struct ths_thermal_chip sun50i_h616_ths = {
|
|
|
|
.sensor_num = 4,
|
|
|
|
.has_bus_clk_reset = true,
|
|
|
|
.needs_sram = true,
|
|
|
|
.ft_deviation = 8000,
|
|
|
|
.offset = 263655,
|
|
|
|
.scale = 810,
|
|
|
|
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
|
|
|
|
.calibrate = sun50i_h6_ths_calibrate,
|
|
|
|
.init = sun50i_h6_thermal_init,
|
|
|
|
.irq_ack = sun50i_h6_irq_ack,
|
|
|
|
.calc_temp = sun8i_ths_calc_temp,
|
|
|
|
};
|
|
|
|
|
2019-12-19 17:28:17 +00:00
|
|
|
static const struct of_device_id of_ths_match[] = {
|
|
|
|
{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
|
|
|
|
{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
|
|
|
|
{ .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths },
|
|
|
|
{ .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths },
|
2020-07-24 07:11:43 +00:00
|
|
|
{ .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
|
2019-12-19 17:28:17 +00:00
|
|
|
{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
|
|
|
|
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
|
2023-12-17 21:06:23 +00:00
|
|
|
{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
|
2024-02-19 15:36:38 +00:00
|
|
|
{ .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
|
2019-12-19 17:28:17 +00:00
|
|
|
{ /* sentinel */ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, of_ths_match);
|
|
|
|
|
|
|
|
static struct platform_driver ths_driver = {
|
|
|
|
.probe = sun8i_ths_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "sun8i-thermal",
|
|
|
|
.of_match_table = of_ths_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(ths_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SOC");
|
|
|
|
MODULE_LICENSE("GPL v2");
|