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clk: sunxi-ng: h616: Add clock/reset for GPADC
Add the GPADC required clock and reset which is used for the onboard GPADC. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20240605172049.231108-3-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
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static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
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static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
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@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
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&bus_emac1_clk.common,
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&ts_clk.common,
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&bus_ts_clk.common,
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&bus_gpadc_clk.common,
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&bus_ths_clk.common,
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&spdif_clk.common,
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&bus_spdif_clk.common,
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@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
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[CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw,
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[CLK_TS] = &ts_clk.common.hw,
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[CLK_BUS_TS] = &bus_ts_clk.common.hw,
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[CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
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[CLK_BUS_THS] = &bus_ths_clk.common.hw,
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[CLK_SPDIF] = &spdif_clk.common.hw,
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[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
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@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
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[RST_BUS_EMAC0] = { 0x97c, BIT(16) },
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[RST_BUS_EMAC1] = { 0x97c, BIT(17) },
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[RST_BUS_TS] = { 0x9bc, BIT(16) },
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[RST_BUS_GPADC] = { 0x9ec, BIT(16) },
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[RST_BUS_THS] = { 0x9fc, BIT(16) },
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[RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
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[RST_BUS_DMIC] = { 0xa4c, BIT(16) },
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@ -51,6 +51,6 @@
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#define CLK_BUS_DRAM 56
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#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1)
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#define CLK_NUMBER (CLK_BUS_GPADC + 1)
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#endif /* _CCU_SUN50I_H616_H_ */
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