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clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()
This was found by a static analyzer.
There may be a potential integer overflow issue in
sg2042_pll_recalc_rate(). numerator is defined as u64 while
parent_rate is defined as unsigned long and ctrl_table.fbdiv
is defined as unsigned int. On 32-bit machine, the result of
the calculation will be limited to "u32" without correct casting.
Integer overflow may occur on high-performance systems.
Fixes: 48cf7e0138
("clk: sophgo: Add SG2042 clock driver")
Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20241023145146.13130-1-zichenxie0106@gmail.com
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -153,7 +153,7 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
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sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
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numerator = parent_rate * ctrl_table.fbdiv;
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numerator = (u64)parent_rate * ctrl_table.fbdiv;
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denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
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do_div(numerator, denominator);
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return numerator;
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