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spi: meson-spicc: set SPI clock flag CLK_SET_RATE_PARENT
Add SPI clock flag CLK_SET_RATE_PARENT for using pclk as parent clock. This gives SPI more flexibility in frequency selection. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Link: https://lore.kernel.org/r/20240524-spi_pclk_setparent-v1-1-99e0ce70b66f@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -644,11 +644,13 @@ static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
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snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
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snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
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init.name = name;
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.ops = &clk_fixed_factor_ops;
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init.flags = 0;
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if (spicc->data->has_pclk) {
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if (spicc->data->has_pclk)
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init.flags = CLK_SET_RATE_PARENT;
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parent_data[0].hw = __clk_get_hw(spicc->pclk);
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parent_data[0].hw = __clk_get_hw(spicc->pclk);
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else
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} else {
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init.flags = 0;
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parent_data[0].hw = __clk_get_hw(spicc->core);
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parent_data[0].hw = __clk_get_hw(spicc->core);
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}
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init.num_parents = 1;
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init.num_parents = 1;
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pow2_fixed_div->mult = 1,
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pow2_fixed_div->mult = 1,
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@ -708,11 +710,13 @@ static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
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snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
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snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
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init.name = name;
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.ops = &clk_fixed_factor_ops;
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init.flags = 0;
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if (spicc->data->has_pclk) {
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if (spicc->data->has_pclk)
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init.flags = CLK_SET_RATE_PARENT;
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parent_data[0].hw = __clk_get_hw(spicc->pclk);
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parent_data[0].hw = __clk_get_hw(spicc->pclk);
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else
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} else {
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init.flags = 0;
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parent_data[0].hw = __clk_get_hw(spicc->core);
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parent_data[0].hw = __clk_get_hw(spicc->core);
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}
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init.num_parents = 1;
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init.num_parents = 1;
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enh_fixed_div->mult = 1,
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enh_fixed_div->mult = 1,
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