mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM updates for v6.9-rc1
- remove a misuse of kernel-doc comment - use "Call trace:" for backtraces like other architectures - implement copy_from_kernel_nofault_allowed() to fix a LKDTM test - add a "cut here" line for prefetch aborts - remove unnecessary Kconfing entry for FRAME_POINTER - remove iwmmxy support for PJ4/PJ4B cores - use bitfield helpers in ptrace to improve readabililty - check if folio is reserved before flushing -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmX5u38ACgkQ9OeQG+St rGTB+xAAh0jUZeBEPUdCEooFPMXpYyTueOrYxth1zqs1UBQNCsfqwfFRY/e8qHgL 8yrpshbgrQY62NCcpHV2Wso9ZUQO7c8JCrI2CpPS+1+oyg/lJN2hPv3i10WmiFgW D0kc4X7hDOn3lapKRRBnWea/Xi7FHl0TTKUfL/+0HrJRtwTW1wPrFk7ECp/vhdIZ KBflQyiAJ2QSlovRBvtr+Fbfdbwd55araArHUSlus43uGnDFQh/h6LYe9gifIO+P SFX4BAo2FfFIhGOJ4ghzPeVL2zfiMRQNButELiktY+KhRSUijOvumnCxRL2YzqJO 0zNzKUWEkShV2NEq82X55zVezQ9wOiB9GYAZRSJ3qAZ3eT2+EqHIPbe2+RnLrKN+ szjCY7S9kKWt4WU0r5P4Au58FjCxJ+gzehvuaE/BYOisGsbejzxoh1uKBf1PR7Xg 3iS+zlYHGo2gfVTNgFpV4nmlgkPelTnyK3+yYAsTr/IAGkMbLHjb6d7qyJZ1Wsde YsRmkXwTkKcE2UlsQB7fGF4S9SrZ6MWqdCvWfCnu3INCMHCEP/8/siXkcX27jRUV o4N2JbioUZmeWPAfcBJnh/aDAzgku63yFev2QgB70awPE5YiOAWRQQIn+mIB1aDV ut9AB1gg/sNe7VnCVAnZEWzlL5DHXqByTXur2FoGjoVWcf1cqv4= =f4r2 -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm Pull ARM updates from Russell King: - remove a misuse of kernel-doc comment - use "Call trace:" for backtraces like other architectures - implement copy_from_kernel_nofault_allowed() to fix a LKDTM test - add a "cut here" line for prefetch aborts - remove unnecessary Kconfing entry for FRAME_POINTER - remove iwmmxy support for PJ4/PJ4B cores - use bitfield helpers in ptrace to improve readabililty - check if folio is reserved before flushing * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 9359/1: flush: check if the folio is reserved for no-mapping addresses ARM: 9354/1: ptrace: Use bitfield helpers ARM: 9352/1: iwmmxt: Remove support for PJ4/PJ4B cores ARM: 9353/1: remove unneeded entry for CONFIG_FRAME_POINTER ARM: 9351/1: fault: Add "cut here" line for prefetch aborts ARM: 9350/1: fault: Implement copy_from_kernel_nofault_allowed() ARM: 9349/1: unwind: Add missing "Call trace:" line ARM: 9334/1: mm: init: remove misuse of kernel-doc comment
This commit is contained in:
Linus Torvalds
commit
02fb638bed
@ -505,8 +505,8 @@ source "arch/arm/mm/Kconfig"
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config IWMMXT
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bool "Enable iWMMXt support"
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depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
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default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
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depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
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default y if PXA27x || PXA3xx || ARCH_MMP
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help
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Enable support for iWMMXt context switching at run time if
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running on a CPU that supports it.
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@ -90,9 +90,6 @@ config BACKTRACE_VERBOSE
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In most cases, say N here, unless you are intending to debug the
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kernel and have access to the kernel binary image.
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config FRAME_POINTER
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bool
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config DEBUG_USER
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bool "Verbose user fault messages"
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help
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@ -10,6 +10,7 @@
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#include <uapi/asm/ptrace.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitfield.h>
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#include <linux/types.h>
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struct pt_regs {
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@ -35,8 +36,8 @@ struct svc_pt_regs {
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#ifndef CONFIG_CPU_V7M
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#define isa_mode(regs) \
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((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \
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(((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))
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(FIELD_GET(PSR_J_BIT, (regs)->ARM_cpsr) << 1 | \
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FIELD_GET(PSR_T_BIT, (regs)->ARM_cpsr))
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#else
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#define isa_mode(regs) 1 /* Thumb */
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#endif
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@ -76,8 +76,6 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
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obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
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obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
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obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
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obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o
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obj-$(CONFIG_IWMMXT) += iwmmxt.o
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obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_xscale.o perf_event_v6.o \
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@ -18,18 +18,6 @@
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#include <asm/assembler.h>
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#include "iwmmxt.h"
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#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
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#define PJ4(code...) code
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#define XSC(code...)
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#elif defined(CONFIG_CPU_MOHAWK) || \
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defined(CONFIG_CPU_XSC3) || \
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defined(CONFIG_CPU_XSCALE)
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#define PJ4(code...)
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#define XSC(code...) code
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#else
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#error "Unsupported iWMMXt architecture"
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#endif
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#define MMX_WR0 (0x00)
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#define MMX_WR1 (0x08)
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#define MMX_WR2 (0x10)
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@ -81,17 +69,13 @@ ENDPROC(iwmmxt_undef_handler)
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ENTRY(iwmmxt_task_enable)
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inc_preempt_count r10, r3
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XSC(mrc p15, 0, r2, c15, c1, 0)
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PJ4(mrc p15, 0, r2, c1, c0, 2)
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mrc p15, 0, r2, c15, c1, 0
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@ CP0 and CP1 accessible?
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XSC(tst r2, #0x3)
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PJ4(tst r2, #0xf)
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tst r2, #0x3
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bne 4f @ if so no business here
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@ enable access to CP0 and CP1
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XSC(orr r2, r2, #0x3)
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XSC(mcr p15, 0, r2, c15, c1, 0)
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PJ4(orr r2, r2, #0xf)
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PJ4(mcr p15, 0, r2, c1, c0, 2)
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orr r2, r2, #0x3
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mcr p15, 0, r2, c15, c1, 0
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ldr r3, =concan_owner
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ldr r2, [r0, #S_PC] @ current task pc value
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@ -218,12 +202,9 @@ ENTRY(iwmmxt_task_disable)
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bne 1f @ no: quit
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@ enable access to CP0 and CP1
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XSC(mrc p15, 0, r4, c15, c1, 0)
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XSC(orr r4, r4, #0x3)
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XSC(mcr p15, 0, r4, c15, c1, 0)
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PJ4(mrc p15, 0, r4, c1, c0, 2)
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PJ4(orr r4, r4, #0xf)
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PJ4(mcr p15, 0, r4, c1, c0, 2)
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mrc p15, 0, r4, c15, c1, 0
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orr r4, r4, #0x3
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mcr p15, 0, r4, c15, c1, 0
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mov r0, #0 @ nothing to load
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str r0, [r3] @ no more current owner
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@ -232,10 +213,8 @@ ENTRY(iwmmxt_task_disable)
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bl concan_save
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@ disable access to CP0 and CP1
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XSC(bic r4, r4, #0x3)
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XSC(mcr p15, 0, r4, c15, c1, 0)
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PJ4(bic r4, r4, #0xf)
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PJ4(mcr p15, 0, r4, c1, c0, 2)
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bic r4, r4, #0x3
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mcr p15, 0, r4, c15, c1, 0
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mrc p15, 0, r2, c2, c0, 0
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mov r2, r2 @ cpwait
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@ -330,11 +309,9 @@ ENDPROC(iwmmxt_task_restore)
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*/
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ENTRY(iwmmxt_task_switch)
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XSC(mrc p15, 0, r1, c15, c1, 0)
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PJ4(mrc p15, 0, r1, c1, c0, 2)
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mrc p15, 0, r1, c15, c1, 0
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@ CP0 and CP1 accessible?
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XSC(tst r1, #0x3)
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PJ4(tst r1, #0xf)
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tst r1, #0x3
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bne 1f @ yes: block them for next task
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ldr r2, =concan_owner
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@ -344,10 +321,8 @@ ENTRY(iwmmxt_task_switch)
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retne lr @ no: leave Concan disabled
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1: @ flip Concan access
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XSC(eor r1, r1, #0x3)
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XSC(mcr p15, 0, r1, c15, c1, 0)
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PJ4(eor r1, r1, #0xf)
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PJ4(mcr p15, 0, r1, c1, c0, 2)
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eor r1, r1, #0x3
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mcr p15, 0, r1, c15, c1, 0
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mrc p15, 0, r1, c2, c0, 0
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sub pc, lr, r1, lsr #32 @ cpwait and return
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@ -1,135 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/kernel/pj4-cp0.c
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*
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* PJ4 iWMMXt coprocessor context switching and handling
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*
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* Copyright (c) 2010 Marvell International Inc.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/thread_notify.h>
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#include <asm/cputype.h>
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static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
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{
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struct thread_info *thread = t;
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switch (cmd) {
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case THREAD_NOTIFY_FLUSH:
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/*
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* flush_thread() zeroes thread->fpstate, so no need
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* to do anything here.
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*
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* FALLTHROUGH: Ensure we don't try to overwrite our newly
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* initialised state information on the first fault.
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*/
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case THREAD_NOTIFY_EXIT:
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iwmmxt_task_release(thread);
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break;
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case THREAD_NOTIFY_SWITCH:
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iwmmxt_task_switch(thread);
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break;
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
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.notifier_call = iwmmxt_do,
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};
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static u32 __init pj4_cp_access_read(void)
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{
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u32 value;
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__asm__ __volatile__ (
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"mrc p15, 0, %0, c1, c0, 2\n\t"
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: "=r" (value));
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return value;
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}
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static void __init pj4_cp_access_write(u32 value)
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{
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u32 temp;
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__asm__ __volatile__ (
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"mcr p15, 0, %1, c1, c0, 2\n\t"
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#ifdef CONFIG_THUMB2_KERNEL
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"isb\n\t"
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#else
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"mrc p15, 0, %0, c1, c0, 2\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4\n\t"
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#endif
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: "=r" (temp) : "r" (value));
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}
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static int __init pj4_get_iwmmxt_version(void)
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{
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u32 cp_access, wcid;
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cp_access = pj4_cp_access_read();
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pj4_cp_access_write(cp_access | 0xf);
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/* check if coprocessor 0 and 1 are available */
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if ((pj4_cp_access_read() & 0xf) != 0xf) {
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pj4_cp_access_write(cp_access);
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return -ENODEV;
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}
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/* read iWMMXt coprocessor id register p1, c0 */
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__asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
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pj4_cp_access_write(cp_access);
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/* iWMMXt v1 */
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if ((wcid & 0xffffff00) == 0x56051000)
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return 1;
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/* iWMMXt v2 */
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if ((wcid & 0xffffff00) == 0x56052000)
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return 2;
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return -EINVAL;
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}
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/*
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* Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
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* switch code handle iWMMXt context switching.
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*/
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static int __init pj4_cp0_init(void)
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{
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u32 __maybe_unused cp_access;
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int vers;
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if (!cpu_is_pj4())
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return 0;
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vers = pj4_get_iwmmxt_version();
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if (vers < 0)
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return 0;
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#ifndef CONFIG_IWMMXT
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pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
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#else
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cp_access = pj4_cp_access_read() & ~0xf;
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pj4_cp_access_write(cp_access);
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pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
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elf_hwcap |= HWCAP_IWMMXT;
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thread_register_notifier(&iwmmxt_notifier_block);
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register_iwmmxt_undef_handler();
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#endif
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return 0;
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}
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late_initcall(pj4_cp0_init);
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@ -220,7 +220,7 @@ void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
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unsigned int fp, mode;
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int ok = 1;
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printk("%sBacktrace: ", loglvl);
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printk("%sCall trace: ", loglvl);
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if (!tsk)
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tsk = current;
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@ -524,6 +524,8 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk,
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{
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struct stackframe frame;
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printk("%sCall trace: ", loglvl);
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pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
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if (!tsk)
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@ -25,6 +25,13 @@
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#include "fault.h"
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bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
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{
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unsigned long addr = (unsigned long)unsafe_src;
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return addr >= TASK_SIZE && ULONG_MAX - addr >= size;
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}
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#ifdef CONFIG_MMU
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/*
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@ -588,6 +595,7 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
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if (!inf->fn(addr, ifsr | FSR_LNX_PF, regs))
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return;
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pr_alert("8<--- cut here ---\n");
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pr_alert("Unhandled prefetch abort: %s (0x%03x) at 0x%08lx\n",
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inf->name, ifsr, addr);
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@ -296,6 +296,9 @@ void __sync_icache_dcache(pte_t pteval)
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return;
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folio = page_folio(pfn_to_page(pfn));
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if (folio_test_reserved(folio))
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return;
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if (cache_is_vipt_aliasing())
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mapping = folio_flush_mapping(folio);
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else
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@ -418,7 +418,7 @@ static void set_section_perms(struct section_perm *perms, int n, bool set,
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}
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/**
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/*
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* update_sections_early intended to be called only through stop_machine
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* framework and executed by only one CPU while all other CPUs will spin and
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* wait, so no locking is required in this function.
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