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mips: ralink: mt7620: remove clock related code
A proper clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Since this is the last clock related code removal, remove also remaining prototypes in 'common.h' header file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Sergio Paracuellos
Thomas Bogendoerfer
parent
7cd1bb4888
commit
04b153abdf
@ -20,52 +20,17 @@
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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#define SYSC_REG_CLKCFG0 0x2c
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#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
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#define SYSC_REG_CPLL_CONFIG0 0x54
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#define SYSC_REG_CPLL_CONFIG1 0x58
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#define MT7620_CHIP_NAME0 0x3637544d
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#define MT7620_CHIP_NAME1 0x20203032
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#define MT7628_CHIP_NAME1 0x20203832
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#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
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#define CHIP_REV_PKG_MASK 0x1
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#define CHIP_REV_PKG_SHIFT 16
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#define CHIP_REV_VER_MASK 0xf
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#define CHIP_REV_VER_SHIFT 8
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#define CHIP_REV_ECO_MASK 0xf
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#define CLKCFG0_PERI_CLK_SEL BIT(4)
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#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
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#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
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#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
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#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
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#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
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#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
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#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
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#define CPLL_CFG0_SW_CFG BIT(31)
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#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
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#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
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#define CPLL_CFG0_LC_CURFCK BIT(15)
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#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
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#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
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#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
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#define CPLL_CFG1_CPU_AUX1 BIT(25)
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#define CPLL_CFG1_CPU_AUX0 BIT(24)
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#define SYSCFG0_DRAM_TYPE_MASK 0x3
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#define SYSCFG0_DRAM_TYPE_SHIFT 4
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#define SYSCFG0_DRAM_TYPE_SDRAM 0
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@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
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extern void ralink_of_remap(void);
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extern void ralink_clk_init(void);
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extern void ralink_clk_add(const char *dev, unsigned long rate);
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extern void ralink_rst_init(void);
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extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
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@ -36,12 +36,6 @@
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#define PMU1_CFG 0x8C
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#define DIG_SW_SEL BIT(25)
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/* clock scaling */
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#define CLKCFG_FDIV_MASK 0x1f00
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#define CLKCFG_FDIV_USB_VAL 0x0300
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#define CLKCFG_FFRAC_MASK 0x001f
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#define CLKCFG_FFRAC_USB_VAL 0x0003
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/* EFUSE bits */
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#define EFUSE_MT7688 0x100000
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@ -53,226 +47,6 @@ static int dram_type;
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static struct ralink_soc_info *soc_info_ptr;
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static __init u32
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mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
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{
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u64 t;
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t = ref_rate;
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t *= mul;
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do_div(t, div);
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return t;
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}
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#define MHZ(x) ((x) * 1000 * 1000)
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static __init unsigned long
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mt7620_get_xtal_rate(void)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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if (reg & SYSCFG0_XTAL_FREQ_SEL)
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return MHZ(40);
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return MHZ(20);
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}
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static __init unsigned long
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mt7620_get_periph_rate(unsigned long xtal_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
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if (reg & CLKCFG0_PERI_CLK_SEL)
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return xtal_rate;
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return MHZ(40);
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}
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static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
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static __init unsigned long
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mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
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if (reg & CPLL_CFG0_BYPASS_REF_CLK)
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return xtal_rate;
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if ((reg & CPLL_CFG0_SW_CFG) == 0)
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return MHZ(600);
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mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
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CPLL_CFG0_PLL_MULT_RATIO_MASK;
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mul += 24;
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if (reg & CPLL_CFG0_LC_CURFCK)
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mul *= 2;
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div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
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CPLL_CFG0_PLL_DIV_RATIO_MASK;
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WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
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return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
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}
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static __init unsigned long
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mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
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if (reg & CPLL_CFG1_CPU_AUX1)
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return xtal_rate;
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if (reg & CPLL_CFG1_CPU_AUX0)
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return MHZ(480);
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return cpu_pll_rate;
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}
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static __init unsigned long
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mt7620_get_cpu_rate(unsigned long pll_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
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div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
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CPU_SYS_CLKCFG_CPU_FDIV_MASK;
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return mt7620_calc_rate(pll_rate, mul, div);
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}
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static const u32 mt7620_ocp_dividers[16] __initconst = {
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[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
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[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
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[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
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[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
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[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
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};
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static __init unsigned long
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mt7620_get_dram_rate(unsigned long pll_rate)
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{
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if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
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return pll_rate / 4;
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return pll_rate / 3;
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}
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static __init unsigned long
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mt7620_get_sys_rate(unsigned long cpu_rate)
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{
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u32 reg;
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u32 ocp_ratio;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
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CPU_SYS_CLKCFG_OCP_RATIO_MASK;
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if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
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return cpu_rate;
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div = mt7620_ocp_dividers[ocp_ratio];
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if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
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return cpu_rate;
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return cpu_rate / div;
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}
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void __init ralink_clk_init(void)
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{
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unsigned long xtal_rate;
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unsigned long cpu_pll_rate;
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unsigned long pll_rate;
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unsigned long cpu_rate;
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unsigned long sys_rate;
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unsigned long dram_rate;
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unsigned long periph_rate;
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unsigned long pcmi2s_rate;
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xtal_rate = mt7620_get_xtal_rate();
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#define RFMT(label) label ":%lu.%03luMHz "
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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if (is_mt76x8()) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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cpu_rate = MHZ(575);
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dram_rate = sys_rate = cpu_rate / 3;
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periph_rate = MHZ(40);
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pcmi2s_rate = MHZ(480);
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ralink_clk_add("10000d00.uartlite", periph_rate);
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ralink_clk_add("10000e00.uartlite", periph_rate);
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} else {
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cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
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pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
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cpu_rate = mt7620_get_cpu_rate(pll_rate);
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dram_rate = mt7620_get_dram_rate(pll_rate);
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sys_rate = mt7620_get_sys_rate(cpu_rate);
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periph_rate = mt7620_get_periph_rate(xtal_rate);
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pcmi2s_rate = periph_rate;
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pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
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RINT(xtal_rate), RFRAC(xtal_rate),
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RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
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RINT(pll_rate), RFRAC(pll_rate));
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ralink_clk_add("10000500.uart", periph_rate);
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}
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pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
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RINT(cpu_rate), RFRAC(cpu_rate),
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RINT(dram_rate), RFRAC(dram_rate),
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RINT(sys_rate), RFRAC(sys_rate),
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RINT(periph_rate), RFRAC(periph_rate));
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#undef RFRAC
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#undef RINT
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#undef RFMT
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000120.watchdog", periph_rate);
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ralink_clk_add("10000900.i2c", periph_rate);
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ralink_clk_add("10000a00.i2s", pcmi2s_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10000d00.uart1", periph_rate);
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ralink_clk_add("10000e00.uart2", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be
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* too low for USB to function properly. Adjust the busses
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* fractional divider to fix this
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*/
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u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
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val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
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rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
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}
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
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