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pinctrl: s32: add missing pins definitions

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Added definitions for some pins which were missing from the
S32G2 SIUL2 pinctrl driver. These pins are used by the JTAG,
PFE and LLCE hardware modules.

Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
Link: https://lore.kernel.org/20241002135920.3647322-2-andrei.stefanescu@oss.nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andrei Stefanescu 2024-10-02 16:59:18 +03:00 committed by Linus Walleij
parent 573cba2827
commit 07963c0206
1 changed files with 52 additions and 0 deletions
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52
drivers/pinctrl/nxp/pinctrl-s32g2.c
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@ -216,6 +216,12 @@ enum s32_pins {
S32G_IMCR_CAN1_RXD = 631,
S32G_IMCR_CAN2_RXD = 632,
S32G_IMCR_CAN3_RXD = 633,
/* JTAG IMCRs */
S32G_IMCR_JTAG_TMS = 562,
S32G_IMCR_JTAG_TCK = 572,
S32G_IMCR_JTAG_TDI = 573,
/* GMAC0 */
S32G_IMCR_Ethernet_MDIO = 527,
S32G_IMCR_Ethernet_CRS = 526,
@ -229,7 +235,21 @@ enum s32_pins {
S32G_IMCR_Ethernet_RX_DV = 530,
S32G_IMCR_Ethernet_TX_CLK = 538,
S32G_IMCR_Ethernet_REF_CLK = 535,
/* PFE EMAC 0 MII */
S32G_IMCR_PFE_EMAC_0_MDIO = 837,
S32G_IMCR_PFE_EMAC_0_CRS = 836,
S32G_IMCR_PFE_EMAC_0_COL = 835,
S32G_IMCR_PFE_EMAC_0_RX_D0 = 841,
S32G_IMCR_PFE_EMAC_0_RX_D1 = 842,
S32G_IMCR_PFE_EMAC_0_RX_D2 = 843,
S32G_IMCR_PFE_EMAC_0_RX_D3 = 844,
S32G_IMCR_PFE_EMAC_0_RX_ER = 840,
S32G_IMCR_PFE_EMAC_0_RX_CLK = 839,
S32G_IMCR_PFE_EMAC_0_RX_DV = 845,
S32G_IMCR_PFE_EMAC_0_TX_CLK = 846,
S32G_IMCR_PFE_EMAC_0_REF_CLK = 838,
/* PFE EMAC 1 MII */
S32G_IMCR_PFE_EMAC_1_MDIO = 857,
S32G_IMCR_PFE_EMAC_1_CRS = 856,
@ -317,6 +337,13 @@ enum s32_pins {
S32G_IMCR_LLCE_CAN13_RXD = 758,
S32G_IMCR_LLCE_CAN14_RXD = 759,
S32G_IMCR_LLCE_CAN15_RXD = 760,
S32G_IMCR_LLCE_UART0_RXD = 790,
S32G_IMCR_LLCE_UART1_RXD = 791,
S32G_IMCR_LLCE_UART2_RXD = 792,
S32G_IMCR_LLCE_UART3_RXD = 793,
S32G_IMCR_LLCE_LPSPI2_PCS0 = 811,
S32G_IMCR_LLCE_LPSPI2_SCK = 816,
S32G_IMCR_LLCE_LPSPI2_SIN = 817,
S32G_IMCR_USB_CLK = 895,
S32G_IMCR_USB_DATA0 = 896,
S32G_IMCR_USB_DATA1 = 897,
@ -503,6 +530,12 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = {
S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7),
S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS),
S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD),
/* JTAG IMCRs */
S32_PINCTRL_PIN(S32G_IMCR_JTAG_TMS),
S32_PINCTRL_PIN(S32G_IMCR_JTAG_TCK),
S32_PINCTRL_PIN(S32G_IMCR_JTAG_TDI),
/* GMAC0 */
S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO),
S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS),
@ -638,6 +671,13 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = {
S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART0_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART1_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART2_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART3_RXD),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_PCS0),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SCK),
S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SIN),
S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD),
S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD),
S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD),
@ -652,6 +692,18 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = {
S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7),
S32_PINCTRL_PIN(S32G_IMCR_USB_DIR),
S32_PINCTRL_PIN(S32G_IMCR_USB_NXT),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_MDIO),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_CRS),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_COL),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D0),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D1),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D2),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D3),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_ER),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_CLK),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_DV),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_TX_CLK),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_REF_CLK),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS),
S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL),