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powerpc: Fix typos
Fix typos, most reported by "codespell arch/powerpc". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20240103231605.1801364-8-helgaas@kernel.org
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@ -108,8 +108,8 @@ DTC_FLAGS ?= -p 1024
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# these files into the build dir, fix up any includes and ensure that dependent
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# files are copied in the right order.
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# these need to be seperate variables because they are copied out of different
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# directories in the kernel tree. Sure you COULd merge them, but it's a
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# these need to be separate variables because they are copied out of different
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# directories in the kernel tree. Sure you COULD merge them, but it's a
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# cure-is-worse-than-disease situation.
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zlib-decomp-$(CONFIG_KERNEL_GZIP) := decompress_inflate.c
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zlib-$(CONFIG_KERNEL_GZIP) := inffast.c inflate.c inftrees.c
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@ -172,7 +172,7 @@
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reg = <0xef602800 0x60>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x4 0x4>;
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/* This thing is a bit weird. It has it's own UIC
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/* This thing is a bit weird. It has its own UIC
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* that it uses to generate snapshot triggers. We
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* don't really support this device yet, and it needs
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* work to figure this out.
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@ -188,7 +188,7 @@ static inline void prep_esm_blob(struct addr_range vmlinux, void *chosen) { }
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/* A buffer that may be edited by tools operating on a zImage binary so as to
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* edit the command line passed to vmlinux (by setting /chosen/bootargs).
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* The buffer is put in it's own section so that tools may locate it easier.
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* The buffer is put in its own section so that tools may locate it easier.
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*/
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static char cmdline[BOOT_COMMAND_LINE_SIZE]
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__attribute__((__section__("__builtin_cmdline")));
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@ -25,7 +25,7 @@ BSS_STACK(4096);
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/* A buffer that may be edited by tools operating on a zImage binary so as to
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* edit the command line passed to vmlinux (by setting /chosen/bootargs).
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* The buffer is put in it's own section so that tools may locate it easier.
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* The buffer is put in its own section so that tools may locate it easier.
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*/
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static char cmdline[BOOT_COMMAND_LINE_SIZE]
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@ -982,7 +982,7 @@ static inline phys_addr_t page_to_phys(struct page *page)
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}
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/*
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* 32 bits still uses virt_to_bus() for it's implementation of DMA
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* 32 bits still uses virt_to_bus() for its implementation of DMA
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* mappings se we have to keep it defined here. We also have some old
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* drivers (shame shame shame) that use bus_to_virt() and haven't been
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* fixed yet so I need to define it here.
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@ -1027,10 +1027,10 @@ struct opal_i2c_request {
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* The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
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* with individual elements being 16 bits wide to fetch the system
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* wide EPOW status. Each element in the buffer will contain the
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* EPOW status in it's bit representation for a particular EPOW sub
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* EPOW status in its bit representation for a particular EPOW sub
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* class as defined here. So multiple detailed EPOW status bits
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* specific for any sub class can be represented in a single buffer
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* element as it's bit representation.
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* element as its bit representation.
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*/
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/* System EPOW type */
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@ -192,7 +192,7 @@ static inline long pmac_call_feature(int selector, struct device_node* node,
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/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
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* enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
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* it's reset line
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* its reset line
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*/
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#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
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@ -144,7 +144,7 @@
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#define UNI_N_HWINIT_STATE_SLEEPING 0x01
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#define UNI_N_HWINIT_STATE_RUNNING 0x02
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/* This last bit appear to be used by the bootROM to know the second
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* CPU has started and will enter it's sleep loop with IP=0
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* CPU has started and will enter its sleep loop with IP=0
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*/
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#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
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@ -108,7 +108,7 @@ typedef struct boot_infos
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/* ALL BELOW NEW (vers. 4) */
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/* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
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(non-PCI) only. On PCI, memory is contiguous and it's size is in the
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(non-PCI) only. On PCI, memory is contiguous and its size is in the
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device-tree. */
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boot_info_map_entry_t
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physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
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@ -527,7 +527,7 @@ EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
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* eeh_pe_mark_isolated
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* @pe: EEH PE
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*
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* Record that a PE has been isolated by marking the PE and it's children as
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* Record that a PE has been isolated by marking the PE and its children as
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* EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices
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* as pci_channel_io_frozen.
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*/
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@ -681,7 +681,7 @@ void crash_fadump(struct pt_regs *regs, const char *str)
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* old_cpu == -1 means this is the first CPU which has come here,
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* go ahead and trigger fadump.
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*
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* old_cpu != -1 means some other CPU has already on it's way
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* old_cpu != -1 means some other CPU has already on its way
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* to trigger fadump, just keep looping here.
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*/
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this_cpu = smp_processor_id();
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@ -192,7 +192,7 @@ _GLOBAL(scom970_read)
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xori r0,r0,MSR_EE
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mtmsrd r0,1
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
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/* rotate 24 bits SCOM address 8 bits left and mask out its low 8 bits
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* (including parity). On current CPUs they must be 0'd,
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* and finally or in RW bit
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*/
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@ -226,7 +226,7 @@ _GLOBAL(scom970_write)
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xori r0,r0,MSR_EE
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mtmsrd r0,1
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
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/* rotate 24 bits SCOM address 8 bits left and mask out its low 8 bits
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* (including parity). On current CPUs they must be 0'd.
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*/
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@ -1661,7 +1661,7 @@ void arch_setup_new_exec(void)
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* cases will happen:
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*
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* 1. The correct thread is running, the wrong thread is not
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* In this situation, the correct thread is woken and proceeds to pass it's
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* In this situation, the correct thread is woken and proceeds to pass its
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* condition check.
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*
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* 2. Neither threads are running
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@ -1671,15 +1671,15 @@ void arch_setup_new_exec(void)
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* for the wrong thread, or they will execute the condition check immediately.
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*
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* 3. The wrong thread is running, the correct thread is not
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* The wrong thread will be woken, but will fail it's condition check and
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* The wrong thread will be woken, but will fail its condition check and
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* re-execute wait. The correct thread, when scheduled, will execute either
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* it's condition check (which will pass), or wait, which returns immediately
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* when called the first time after the thread is scheduled, followed by it's
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* its condition check (which will pass), or wait, which returns immediately
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* when called the first time after the thread is scheduled, followed by its
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* condition check (which will pass).
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*
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* 4. Both threads are running
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* Both threads will be woken. The wrong thread will fail it's condition check
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* and execute another wait, while the correct thread will pass it's condition
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* Both threads will be woken. The wrong thread will fail its condition check
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* and execute another wait, while the correct thread will pass its condition
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* check.
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*
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* @t: the task to set the thread ID for
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@ -12,7 +12,7 @@ void flush_tmregs_to_thread(struct task_struct *tsk)
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{
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/*
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* If task is not current, it will have been flushed already to
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* it's thread_struct during __switch_to().
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* its thread_struct during __switch_to().
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*
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* A reclaim flushes ALL the state or if not in TM save TM SPRs
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* in the appropriate thread structures from live.
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@ -1567,7 +1567,7 @@ static void add_cpu_to_masks(int cpu)
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/*
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* This CPU will not be in the online mask yet so we need to manually
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* add it to it's own thread sibling mask.
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* add it to its own thread sibling mask.
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*/
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map_cpu_to_node(cpu, cpu_to_node(cpu));
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cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
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@ -139,7 +139,7 @@ static unsigned long dscr_default;
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* @val: Returned cpu specific DSCR default value
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*
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* This function returns the per cpu DSCR default value
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* for any cpu which is contained in it's PACA structure.
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* for any cpu which is contained in its PACA structure.
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*/
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static void read_dscr(void *val)
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{
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@ -152,7 +152,7 @@ static void read_dscr(void *val)
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* @val: New cpu specific DSCR default value to update
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*
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* This function updates the per cpu DSCR default value
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* for any cpu which is contained in it's PACA structure.
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* for any cpu which is contained in its PACA structure.
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*/
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static void write_dscr(void *val)
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{
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@ -531,7 +531,7 @@ static int xive_vm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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xc->cppr = xive_prio_from_guest(new_cppr);
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/*
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* IPIs are synthetized from MFRR and thus don't need
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* IPIs are synthesized from MFRR and thus don't need
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* any special EOI handling. The underlying interrupt
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* used to signal MFRR changes is EOId when fetched from
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* the queue.
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@ -78,7 +78,7 @@ EXPORT_SYMBOL(flush_icache_range);
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#ifdef CONFIG_HIGHMEM
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/**
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* flush_dcache_icache_phys() - Flush a page by it's physical address
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* flush_dcache_icache_phys() - Flush a page by its physical address
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* @physaddr: the physical address of the page
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*/
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static void flush_dcache_icache_phys(unsigned long physaddr)
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@ -376,7 +376,7 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
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create_kaslr_tlb_entry(1, tlb_virt, tlb_phys);
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}
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/* Copy the kernel to it's new location and run */
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/* Copy the kernel to its new location and run */
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memcpy((void *)kernstart_virt_addr, (void *)_stext, kernel_sz);
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flush_icache_range(kernstart_virt_addr, kernstart_virt_addr + kernel_sz);
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@ -279,7 +279,7 @@ static void __init mpc512x_setup_diu(void)
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* and so negatively affect boot time. Instead we reserve the
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* already configured frame buffer area so that it won't be
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* destroyed. The starting address of the area to reserve and
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* also it's length is passed to memblock_reserve(). It will be
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* also its length is passed to memblock_reserve(). It will be
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* freed later on first open of fbdev, when splash image is not
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* needed any more.
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*/
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@ -868,7 +868,7 @@ static int __spu_deactivate(struct spu_context *ctx, int force, int max_prio)
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}
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/**
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* spu_deactivate - unbind a context from it's physical spu
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* spu_deactivate - unbind a context from its physical spu
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* @ctx: spu context to unbind
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*
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* Unbind @ctx from the physical spu it is running on and schedule
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@ -595,7 +595,7 @@ void __init maple_pci_init(void)
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/* Probe root PCI hosts, that is on U3 the AGP host and the
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* HyperTransport host. That one is actually "kept" around
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* and actually added last as it's resource management relies
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* and actually added last as its resource management relies
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* on the AGP resources to have been setup first
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*/
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root = of_find_node_by_path("/");
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@ -2,7 +2,7 @@
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/*
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* Support for the interrupt controllers found on Power Macintosh,
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* currently Apple's "Grand Central" interrupt controller in all
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* it's incarnations. OpenPIC support used on newer machines is
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* its incarnations. OpenPIC support used on newer machines is
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* in a separate file
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*
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* Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
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@ -176,7 +176,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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* memory location containing the PC to resume from
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* at address 0.
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* - On Core99, we must store the wakeup vector at
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* address 0x80 and eventually it's parameters
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* address 0x80 and eventually its parameters
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* at address 0x84. I've have some trouble with those
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* parameters however and I no longer use them.
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*/
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@ -238,7 +238,7 @@ void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
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} else if (pdev->is_physfn) {
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/*
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* For PFs adjust their allocated IOV resources to match what
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* the PHB can support using it's M64 BAR table.
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* the PHB can support using its M64 BAR table.
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*/
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pnv_pci_ioda_fixup_iov_resources(pdev);
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}
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@ -658,7 +658,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
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list_add_tail(&pe->list, &phb->ioda.pe_list);
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mutex_unlock(&phb->ioda.pe_list_mutex);
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/* associate this pe to it's pdn */
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/* associate this pe to its pdn */
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list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
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if (vf_pdn->busno == vf_bus &&
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vf_pdn->devfn == vf_devfn) {
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@ -1059,7 +1059,7 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
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}
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} else {
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/*
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* Interrupt hanlder or fault window setup failed. Means
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* Interrupt handler or fault window setup failed. Means
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* NX can not generate fault for page fault. So not
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* opening for user space tx window.
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*/
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@ -228,7 +228,7 @@ static irqreturn_t pseries_vas_irq_handler(int irq, void *data)
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struct pseries_vas_window *txwin = data;
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/*
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* The thread hanlder will process this interrupt if it is
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* The thread handler will process this interrupt if it is
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* already running.
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*/
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atomic_inc(&txwin->pending_faults);
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@ -383,7 +383,7 @@ static unsigned int xive_get_irq(void)
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* CPU.
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*
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* If we find that there is indeed more in there, we call
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* force_external_irq_replay() to make Linux synthetize an
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* force_external_irq_replay() to make Linux synthesize an
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* external interrupt on the next call to local_irq_restore().
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*/
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static void xive_do_queue_eoi(struct xive_cpu *xc)
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@ -874,7 +874,7 @@ static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
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*
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* This also tells us that it's in flight to a host queue
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* or has already been fetched but hasn't been EOIed yet
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* by the host. This it's potentially using up a host
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* by the host. Thus it's potentially using up a host
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* queue slot. This is important to know because as long
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* as this is the case, we must not hard-unmask it when
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* "returning" that interrupt to the host.
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@ -415,7 +415,7 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
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return;
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}
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/* Grab it's CAM value */
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/* Grab its CAM value */
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rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
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if (rc) {
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pr_err("Failed to get pool VP info CPU %d\n", cpu);
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