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Merge branches 'clk-stm', 'clk-cleanup', 'clk-kunit' and 'clk-mediatek' into clk-next

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- Add reset support to Airoha EN7581 clk driver
 - Add module description to mediatek clk drivers

* clk-stm:
  clk: stm32mp25: add security clocks
  clk: stm32mp2: use of STM32 access controller

* clk-cleanup:
  clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
  clk: lpc32xx: Constify struct regmap_config
  clk: xilinx: Constify struct regmap_config
  dt-bindings: clock: sprd,sc9860-clk: convert to YAML
  dt-bindings: clock: qoriq-clock: convert to yaml format
  clk: vexpress-osc: add missing MODULE_DESCRIPTION() macro
  clk: sifive: prci: fix module autoloading
  dt-bindings: clock: milbeaut: Drop providers and consumers from example
  clk: sprd: add missing MODULE_DESCRIPTION() macro
  clk: sophgo: add missing MODULE_DESCRIPTION() macro

* clk-kunit:
  clk: disable clk gate tests for s390
  clk: test: add missing MODULE_DESCRIPTION() macros

* clk-mediatek:
  clk: en7523: fix rate divider for slic and spi clocks
  clk: en7523: Remove PCIe reset open drain configuration for EN7581
  clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
  clk: en7523: Add reset-controller support for EN7581 SoC
  dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
  dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
  clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
  dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
  clk: mediatek: Add a module description where missing
This commit is contained in:
Stephen Boyd 2024-07-16 11:24:01 -07:00
commit 160d7b9fb9
169 changed files with 1065 additions and 390 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
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@ -35,7 +35,7 @@ properties:
reg:
minItems: 2
maxItems: 3
maxItems: 4
"#clock-cells":
description:
@ -43,6 +43,10 @@ properties:
clocks.
const: 1
'#reset-cells':
description: ID of the controller reset line
const: 1
required:
- compatible
- reg
@ -60,6 +64,8 @@ allOf:
- description: scu base address
- description: misc scu base address
'#reset-cells': false
- if:
properties:
compatible:
@ -70,6 +76,7 @@ allOf:
items:
- description: scu base address
- description: misc scu base address
- description: reset base address
- description: pb scu base address
additionalProperties: false
@ -83,3 +90,19 @@ examples:
<0x1fb00000 0x1000>;
#clock-cells = <1>;
};
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
scuclk: clock-controller@1fa20000 {
compatible = "airoha,en7581-scu";
reg = <0x0 0x1fa20000 0x0 0x400>,
<0x0 0x1fb00000 0x0 0x90>,
<0x0 0x1fb00830 0x0 0x8>,
<0x0 0x1fbe3400 0x0 0xfc>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

84
Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml Normal file
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@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Legacy Clock Block on Freescale QorIQ Platforms
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
These nodes are deprecated. Kernels should continue to support
device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
properties:
compatible:
enum:
- fsl,qoriq-core-pll-1.0
- fsl,qoriq-core-pll-2.0
- fsl,qoriq-core-mux-1.0
- fsl,qoriq-core-mux-2.0
- fsl,qoriq-sysclk-1.0
- fsl,qoriq-sysclk-2.0
- fsl,qoriq-platform-pll-1.0
- fsl,qoriq-platform-pll-2.0
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
clock-output-names:
minItems: 1
maxItems: 8
'#clock-cells':
minimum: 0
maximum: 1
required:
- compatible
- '#clock-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,qoriq-sysclk-1.0
- fsl,qoriq-sysclk-2.0
then:
properties:
'#clock-cells':
const: 0
- if:
properties:
compatible:
contains:
enum:
- fsl,qoriq-core-pll-1.0
- fsl,qoriq-core-pll-2.0
then:
properties:
'#clock-cells':
const: 1
description: |
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4

207
Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml Normal file
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@ -0,0 +1,207 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock Block on Freescale QorIQ Platforms
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240
Clock Provider
The clockgen node should act as a clock provider, though in older device
trees the children of the clockgen node are the clock providers.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,p2041-clockgen
- fsl,p3041-clockgen
- fsl,p4080-clockgen
- fsl,p5020-clockgen
- fsl,p5040-clockgen
- const: fsl,qoriq-clockgen-1.0
- items:
- enum:
- fsl,t1023-clockgen
- fsl,t1024-clockgen
- fsl,t1040-clockgen
- fsl,t1042-clockgen
- fsl,t2080-clockgen
- fsl,t2081-clockgen
- fsl,t4240-clockgen
- const: fsl,qoriq-clockgen-2.0
- items:
- enum:
- fsl,b4420-clockgen
- fsl,b4860-clockgen
- const: fsl,b4-clockgen
- items:
- enum:
- fsl,ls1012a-clockgen
- fsl,ls1021a-clockgen
- fsl,ls1028a-clockgen
- fsl,ls1043a-clockgen
- fsl,ls1046a-clockgen
- fsl,ls1088a-clockgen
- fsl,ls2080a-clockgen
- fsl,lx2160a-clockgen
reg:
maxItems: 1
ranges: true
'#address-cells':
const: 1
'#size-cells':
const: 1
'#clock-cells':
const: 2
description: |
The first cell of the clock specifier is the clock type, and the
second cell is the clock index for the specified type.
Type# Name Index Cell
0 sysclk must be 0
1 cmux index (n in CLKCnCSR)
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll n=pll/(n+1). For example, when n=1,
that means output_freq=PLL_freq/2.
5 coreclk must be 0
clock-frequency:
description: Input system clock frequency (SYSCLK)
clocks:
items:
- description:
sysclk may be provided as an input clock. Either clock-frequency
or clocks must be provided.
- description:
A second input clock, called "coreclk", may be provided if
core PLLs are based on a different input clock from the
platform PLL.
minItems: 1
clock-names:
items:
- const: sysclk
- const: coreclk
patternProperties:
'^mux[0-9]@[a-f0-9]+$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
'^sysclk(-[a-z0-9]+)?$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
'^pll[0-9]@[a-f0-9]+$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
'^platform\-pll@[a-f0-9]+$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
/* clock provider example */
global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <133333333>;
#clock-cells = <2>;
};
- |
/* Legacy example */
global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
ranges = <0x0 0xe1000 0x1000>;
clock-frequency = <133333333>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <2>;
sysclk: sysclk {
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
#clock-cells = <0>;
};
pll0: pll0@800 {
compatible = "fsl,qoriq-core-pll-1.0";
reg = <0x800 0x4>;
#clock-cells = <1>;
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
compatible = "fsl,qoriq-core-pll-1.0";
reg = <0x820 0x4>;
#clock-cells = <1>;
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
compatible = "fsl,qoriq-core-mux-1.0";
reg = <0x0 0x4>;
#clock-cells = <0>;
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
compatible = "fsl,qoriq-core-mux-1.0";
reg = <0x20 0x4>;
#clock-cells = <0>;
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};

10
Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
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@ -14,9 +14,11 @@ maintainers:
properties:
compatible:
enum:
- mediatek,mt7622-pciesys
- mediatek,mt7629-pciesys
oneOf:
- items:
- const: mediatek,mt7622-pciesys
- const: syscon
- const: mediatek,mt7629-pciesys
reg:
maxItems: 1
@ -38,7 +40,7 @@ additionalProperties: false
examples:
- |
clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys";
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

3
Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
View File

@ -39,6 +39,9 @@ properties:
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg

29
Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
View File

@ -40,38 +40,11 @@ required:
additionalProperties: false
examples:
# Clock controller node:
- |
m10v-clk-ctrl@1d021000 {
clock-controller@1d021000 {
compatible = "socionext,milbeaut-m10v-ccu";
reg = <0x1d021000 0x4000>;
#clock-cells = <1>;
clocks = <&clki40mhz>;
};
# Required an external clock for Clock controller node:
- |
clocks {
clki40mhz: clki40mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
/* other clocks */
};
# The clock consumer shall specify the desired clock-output of the clock
# controller as below by specifying output-id in its "clk" phandle cell.
# 2: uart
# 4: 32-bit timer
# 7: UHS-I/II
- |
serial@1e700010 {
compatible = "socionext,milbeaut-usio-uart";
reg = <0x1e700010 0x10>;
interrupts = <0 141 0x4>, <0 149 0x4>;
interrupt-names = "rx", "tx";
clocks = <&clk 2>;
};
...

212
Documentation/devicetree/bindings/clock/qoriq-clock.txt
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@ -1,212 +0,0 @@
* Clock Block on Freescale QorIQ Platforms
Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240, b4860
1. Clock Block Binding
Required properties:
- compatible: Should contain a chip-specific clock block compatible
string and (if applicable) may contain a chassis-version clock
compatible string.
Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
* "fsl,p2041-clockgen"
* "fsl,p3041-clockgen"
* "fsl,p4080-clockgen"
* "fsl,p5020-clockgen"
* "fsl,p5040-clockgen"
* "fsl,t1023-clockgen"
* "fsl,t1024-clockgen"
* "fsl,t1040-clockgen"
* "fsl,t1042-clockgen"
* "fsl,t2080-clockgen"
* "fsl,t2081-clockgen"
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1012a-clockgen"
* "fsl,ls1021a-clockgen"
* "fsl,ls1028a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
* "fsl,lx2160a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
address space defined by its parent bus, and resource zero
represents the clock register set
Optional properties:
- ranges: Allows valid translation between child's address space and
parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
physical base addresses. Must be present if the device has
sub-nodes and set to 1 if present
- #size-cells: Specifies the number of cells used to represent
the size of an address. Must be present if the device has
sub-nodes and set to 1 if present
- clock-frequency: Input system clock frequency (SYSCLK)
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
A second input clock, called "coreclk", may be provided if
core PLLs are based on a different input clock from the
platform PLL.
- clock-names: Required if a coreclk is present. Valid names are
"sysclk" and "coreclk".
2. Clock Provider
The clockgen node should act as a clock provider, though in older device
trees the children of the clockgen node are the clock providers.
When the clockgen node is a clock provider, #clock-cells = <2>.
The first cell of the clock specifier is the clock type, and the
second cell is the clock index for the specified type.
Type# Name Index Cell
0 sysclk must be 0
1 cmux index (n in CLKCnCSR)
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll n=pll/(n+1). For example, when n=1,
that means output_freq=PLL_freq/2.
5 coreclk must be 0
3. Example
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
clock-frequency = <133333333>;
reg = <0xe1000 0x1000>;
#clock-cells = <2>;
};
fman@400000 {
...
clocks = <&clockgen 3 0>;
...
};
}
4. Legacy Child Nodes
NOTE: These nodes are deprecated. Kernels should continue to support
device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : Should include one of the following:
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
clock-specifier cell may take the following values:
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4
Recommended properties:
- clocks: Should be the phandle of input parent clock
- clock-names: From common clock binding, indicates the clock name
- clock-output-names: From common clock binding, indicates the names of
output clocks
- reg: Should be the offset and length of clock block base address.
The length should be 4.
Legacy Example:
/ {
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
clock-frequency = <133333333>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform-pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};
};
Example for legacy clock consumer:
/ {
cpu0: PowerPC,e5500@0 {
...
clocks = <&mux0>;
...
};
};

63
Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt
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@ -1,63 +0,0 @@
Spreadtrum SC9860 Clock Binding
------------------------
Required properties:
- compatible: should contain the following compatible strings:
- "sprd,sc9860-pmu-gate"
- "sprd,sc9860-pll"
- "sprd,sc9860-ap-clk"
- "sprd,sc9860-aon-prediv"
- "sprd,sc9860-apahb-gate"
- "sprd,sc9860-aon-gate"
- "sprd,sc9860-aonsecure-clk"
- "sprd,sc9860-agcp-gate"
- "sprd,sc9860-gpu-clk"
- "sprd,sc9860-vsp-clk"
- "sprd,sc9860-vsp-gate"
- "sprd,sc9860-cam-clk"
- "sprd,sc9860-cam-gate"
- "sprd,sc9860-disp-clk"
- "sprd,sc9860-disp-gate"
- "sprd,sc9860-apapb-gate"
- #clock-cells: must be 1
- clocks : Should be the input parent clock(s) phandle for the clock, this
property here just simply shows which clock group the clocks'
parents are in, since each clk node would represent many clocks
which are defined in the driver. The detailed dependency
relationship (i.e. how many parents and which are the parents)
are implemented in driver code.
Optional properties:
- reg: Contain the registers base address and length. It must be configured
only if no 'sprd,syscon' under the node.
- sprd,syscon: phandle to the syscon which is in the same address area with
the clock, and so we can get regmap for the clocks from the
syscon device.
Example:
pmu_gate: pmu-gate {
compatible = "sprd,sc9860-pmu-gate";
sprd,syscon = <&pmu_regs>;
clocks = <&ext_26m>;
#clock-cells = <1>;
};
pll: pll {
compatible = "sprd,sc9860-pll";
sprd,syscon = <&ana_regs>;
clocks = <&pmu_gate 0>;
#clock-cells = <1>;
};
ap_clk: clock-controller@20000000 {
compatible = "sprd,sc9860-ap-clk";
reg = <0 0x20000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>,
<&pmu_gate 0>;
#clock-cells = <1>;
};

159
Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml Normal file
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@ -0,0 +1,159 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spreadtrum SC9860 clock
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
properties:
compatible:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aonsecure-clk
- sprd,sc9860-aon-gate
- sprd,sc9860-aon-prediv
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-ap-clk
- sprd,sc9860-cam-clk
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-clk
- sprd,sc9860-disp-gate
- sprd,sc9860-gpu-clk
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-clk
- sprd,sc9860-vsp-gate
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
'#clock-cells':
const: 1
sprd,syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the syscon which is in the same address area with the
clock, and so we can get regmap for the clocks from the syscon device
required:
- compatible
- clocks
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aon-gate
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-gate
- sprd,sc9860-gpu-clk
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-gate
then:
properties:
clocks:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-aonsecure-clk
- sprd,sc9860-cam-clk
- sprd,sc9860-disp-clk
- sprd,sc9860-vsp-clk
then:
properties:
clocks:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-aon-prediv
- sprd,sc9860-ap-clk
then:
properties:
clocks:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-aonsecure-clk
- sprd,sc9860-aon-prediv
- sprd,sc9860-ap-clk
- sprd,sc9860-cam-clk
- sprd,sc9860-disp-clk
- sprd,sc9860-gpu-clk
- sprd,sc9860-vsp-clk
then:
required:
- reg
properties:
sprd,syscon: false
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aon-gate
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-gate
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-gate
then:
required:
- sprd,syscon
properties:
reg: false
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pmu-gate {
compatible = "sprd,sc9860-pmu-gate";
clocks = <&ext_26m>;
#clock-cells = <1>;
sprd,syscon = <&pmu_regs>;
};
clock-controller@20000000 {
compatible = "sprd,sc9860-ap-clk";
reg = <0 0x20000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>, <&pmu_gate 0>;
#clock-cells = <1>;
};
};
...

1
drivers/clk/Kconfig
View File

@ -514,6 +514,7 @@ config CLK_KUNIT_TEST
config CLK_GATE_KUNIT_TEST
tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS
depends on KUNIT
depends on !S390
default KUNIT_ALL_TESTS
help
Kunit test for the basic clk gate type.

254
drivers/clk/clk-en7523.c
View File

@ -5,7 +5,11 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
#define RST_NR_PER_BANK 32
#define REG_PCI_CONTROL 0x88
#define REG_PCI_CONTROL_PERSTOUT BIT(29)
@ -33,13 +37,14 @@
#define REG_PCIE1_MEM_MASK 0x0c
#define REG_PCIE2_MEM 0x10
#define REG_PCIE2_MEM_MASK 0x14
#define REG_PCIE_RESET_OPEN_DRAIN 0x018c
#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
#define REG_NP_SCU_PCIC 0x88
#define REG_NP_SCU_SSTR 0x9c
#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
#define REG_RST_CTRL2 0x00
#define REG_RST_CTRL1 0x04
struct en_clk_desc {
int id;
const char *name;
@ -57,6 +62,7 @@ struct en_clk_desc {
u8 div_shift;
u16 div_val0;
u8 div_step;
u8 div_offset;
};
struct en_clk_gate {
@ -64,10 +70,21 @@ struct en_clk_gate {
struct clk_hw hw;
};
struct en_rst_data {
const u16 *bank_ofs;
const u16 *idx_map;
void __iomem *base;
struct reset_controller_dev rcdev;
};
struct en_clk_soc_data {
const struct clk_ops pcie_ops;
int (*hw_init)(struct platform_device *pdev, void __iomem *base,
void __iomem *np_base);
struct {
const u16 *bank_ofs;
const u16 *idx_map;
u16 idx_map_nr;
} reset;
int (*hw_init)(struct platform_device *pdev, void __iomem *np_base);
};
static const u32 gsw_base[] = { 400000000, 500000000 };
@ -90,6 +107,7 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_EMI,
.name = "emi",
@ -103,6 +121,7 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_BUS,
.name = "bus",
@ -116,6 +135,7 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_SLIC,
.name = "slic",
@ -156,18 +176,82 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_CRYPTO,
.name = "crypto",
.base_reg = REG_CRYPTO_CLKSRC,
.base_bits = 1,
.base_shift = 8,
.base_shift = 0,
.base_values = emi_base,
.n_base_values = ARRAY_SIZE(emi_base),
}
};
static const u16 en7581_rst_ofs[] = {
REG_RST_CTRL2,
REG_RST_CTRL1,
};
static const u16 en7581_rst_map[] = {
/* RST_CTRL2 */
[EN7581_XPON_PHY_RST] = 0,
[EN7581_CPU_TIMER2_RST] = 2,
[EN7581_HSUART_RST] = 3,
[EN7581_UART4_RST] = 4,
[EN7581_UART5_RST] = 5,
[EN7581_I2C2_RST] = 6,
[EN7581_XSI_MAC_RST] = 7,
[EN7581_XSI_PHY_RST] = 8,
[EN7581_NPU_RST] = 9,
[EN7581_I2S_RST] = 10,
[EN7581_TRNG_RST] = 11,
[EN7581_TRNG_MSTART_RST] = 12,
[EN7581_DUAL_HSI0_RST] = 13,
[EN7581_DUAL_HSI1_RST] = 14,
[EN7581_HSI_RST] = 15,
[EN7581_DUAL_HSI0_MAC_RST] = 16,
[EN7581_DUAL_HSI1_MAC_RST] = 17,
[EN7581_HSI_MAC_RST] = 18,
[EN7581_WDMA_RST] = 19,
[EN7581_WOE0_RST] = 20,
[EN7581_WOE1_RST] = 21,
[EN7581_HSDMA_RST] = 22,
[EN7581_TDMA_RST] = 24,
[EN7581_EMMC_RST] = 25,
[EN7581_SOE_RST] = 26,
[EN7581_PCIE2_RST] = 27,
[EN7581_XFP_MAC_RST] = 28,
[EN7581_USB_HOST_P1_RST] = 29,
[EN7581_USB_HOST_P1_U3_PHY_RST] = 30,
/* RST_CTRL1 */
[EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
[EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
[EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
[EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
[EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6,
[EN7581_TIMER_RST] = RST_NR_PER_BANK + 8,
[EN7581_PCM1_RST] = RST_NR_PER_BANK + 11,
[EN7581_UART_RST] = RST_NR_PER_BANK + 12,
[EN7581_GPIO_RST] = RST_NR_PER_BANK + 13,
[EN7581_GDMA_RST] = RST_NR_PER_BANK + 14,
[EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
[EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
[EN7581_SFC_RST] = RST_NR_PER_BANK + 18,
[EN7581_UART2_RST] = RST_NR_PER_BANK + 19,
[EN7581_GDMP_RST] = RST_NR_PER_BANK + 20,
[EN7581_FE_RST] = RST_NR_PER_BANK + 21,
[EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
[EN7581_GSW_RST] = RST_NR_PER_BANK + 23,
[EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
[EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26,
[EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27,
[EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
[EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
};
static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
{
const struct en_clk_desc *desc = &en7523_base_clks[i];
@ -202,7 +286,7 @@ static u32 en7523_get_div(void __iomem *base, int i)
if (!val && desc->div_val0)
return desc->div_val0;
return (val + 1) * desc->div_step;
return (val + desc->div_offset) * desc->div_step;
}
static int en7523_pci_is_enabled(struct clk_hw *hw)
@ -279,9 +363,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
cg->base = np_base;
cg->hw.init = &init;
if (init.ops->disable)
init.ops->disable(&cg->hw);
init.ops->unprepare(&cg->hw);
if (init.ops->unprepare)
init.ops->unprepare(&cg->hw);
if (clk_hw_register(dev, &cg->hw))
return NULL;
@ -299,23 +382,6 @@ static int en7581_pci_is_enabled(struct clk_hw *hw)
return (val & mask) == mask;
}
static int en7581_pci_prepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
void __iomem *np_base = cg->base;
u32 val, mask;
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
REG_RESET_CONTROL_PCIEHB;
val = readl(np_base + REG_RESET_CONTROL1);
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
val = readl(np_base + REG_RESET_CONTROL2);
writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
usleep_range(5000, 10000);
return 0;
}
static int en7581_pci_enable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
@ -332,23 +398,6 @@ static int en7581_pci_enable(struct clk_hw *hw)
return 0;
}
static void en7581_pci_unprepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
void __iomem *np_base = cg->base;
u32 val, mask;
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
REG_RESET_CONTROL_PCIEHB;
val = readl(np_base + REG_RESET_CONTROL1);
writel(val | mask, np_base + REG_RESET_CONTROL1);
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
writel(val | mask, np_base + REG_RESET_CONTROL1);
val = readl(np_base + REG_RESET_CONTROL2);
writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
msleep(100);
}
static void en7581_pci_disable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
@ -364,13 +413,12 @@ static void en7581_pci_disable(struct clk_hw *hw)
}
static int en7581_clk_hw_init(struct platform_device *pdev,
void __iomem *base,
void __iomem *np_base)
{
void __iomem *pb_base;
u32 val;
pb_base = devm_platform_ioremap_resource(pdev, 2);
pb_base = devm_platform_ioremap_resource(pdev, 3);
if (IS_ERR(pb_base))
return PTR_ERR(pb_base);
@ -387,10 +435,6 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
writel(0x28000000, pb_base + REG_PCIE2_MEM);
writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
base + REG_PCIE_RESET_OPEN_DRAIN);
return 0;
}
@ -423,6 +467,95 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
clk_data->num = EN7523_NUM_CLOCKS;
}
static int en7523_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
u32 val;
val = readl(addr);
if (assert)
val |= BIT(id % RST_NR_PER_BANK);
else
val &= ~BIT(id % RST_NR_PER_BANK);
writel(val, addr);
return 0;
}
static int en7523_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return en7523_reset_update(rcdev, id, true);
}
static int en7523_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return en7523_reset_update(rcdev, id, false);
}
static int en7523_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
}
static int en7523_reset_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
if (reset_spec->args[0] >= rcdev->nr_resets)
return -EINVAL;
return rst_data->idx_map[reset_spec->args[0]];
}
static const struct reset_control_ops en7523_reset_ops = {
.assert = en7523_reset_assert,
.deassert = en7523_reset_deassert,
.status = en7523_reset_status,
};
static int en7523_reset_register(struct platform_device *pdev,
const struct en_clk_soc_data *soc_data)
{
struct device *dev = &pdev->dev;
struct en_rst_data *rst_data;
void __iomem *base;
/* no reset lines available */
if (!soc_data->reset.idx_map_nr)
return 0;
base = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(base))
return PTR_ERR(base);
rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
if (!rst_data)
return -ENOMEM;
rst_data->bank_ofs = soc_data->reset.bank_ofs;
rst_data->idx_map = soc_data->reset.idx_map;
rst_data->base = base;
rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
rst_data->rcdev.of_xlate = en7523_reset_xlate;
rst_data->rcdev.ops = &en7523_reset_ops;
rst_data->rcdev.of_node = dev->of_node;
rst_data->rcdev.of_reset_n_cells = 1;
rst_data->rcdev.owner = THIS_MODULE;
rst_data->rcdev.dev = dev;
return devm_reset_controller_register(dev, &rst_data->rcdev);
}
static int en7523_clk_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
@ -441,7 +574,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
soc_data = device_get_match_data(&pdev->dev);
if (soc_data->hw_init) {
r = soc_data->hw_init(pdev, base, np_base);
r = soc_data->hw_init(pdev, np_base);
if (r)
return r;
}
@ -456,11 +589,17 @@ static int en7523_clk_probe(struct platform_device *pdev)
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
pdev->name);
return r;
r = en7523_reset_register(pdev, soc_data);
if (r) {
of_clk_del_provider(node);
return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
pdev->name);
}
return 0;
}
static const struct en_clk_soc_data en7523_data = {
@ -474,11 +613,14 @@ static const struct en_clk_soc_data en7523_data = {
static const struct en_clk_soc_data en7581_data = {
.pcie_ops = {
.is_enabled = en7581_pci_is_enabled,
.prepare = en7581_pci_prepare,
.enable = en7581_pci_enable,
.unprepare = en7581_pci_unprepare,
.disable = en7581_pci_disable,
},
.reset = {
.bank_ofs = en7581_rst_ofs,
.idx_map = en7581_rst_map,
.idx_map_nr = ARRAY_SIZE(en7581_rst_map),
},
.hw_init = en7581_clk_hw_init,
};

3
drivers/clk/clk-fractional-divider_test.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Kunit test for clock fractional divider
* Kunit tests for clk fractional divider
*/
#include <linux/clk-provider.h>
#include <kunit/test.h>
@ -144,4 +144,5 @@ static struct kunit_suite clk_fd_approximation_suite = {
kunit_test_suites(
&clk_fd_approximation_suite
);
MODULE_DESCRIPTION("Kunit tests for clk fractional divider");
MODULE_LICENSE("GPL");

3
drivers/clk/clk-gate_test.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Kunit test for clk gate basic type
* Kunit tests for clk gate
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
@ -461,4 +461,5 @@ kunit_test_suites(
&clk_gate_test_hiword_suite,
&clk_gate_test_enabled_suite
);
MODULE_DESCRIPTION("Kunit tests for clk gate");
MODULE_LICENSE("GPL v2");

3
drivers/clk/clk_test.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Kunit test for clk rate management
* Kunit tests for clk framework
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
@ -2674,4 +2674,5 @@ kunit_test_suites(
&clk_single_parent_mux_test_suite,
&clk_uncached_test_suite
);
MODULE_DESCRIPTION("Kunit tests for clk framework");
MODULE_LICENSE("GPL v2");

2
drivers/clk/mediatek/clk-mt2701-aud.c
View File

@ -165,4 +165,6 @@ static struct platform_driver clk_mt2701_aud_drv = {
},
};
module_platform_driver(clk_mt2701_aud_drv);
MODULE_DESCRIPTION("MediaTek MT2701 audio clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-bdp.c
View File

@ -106,4 +106,6 @@ static struct platform_driver clk_mt2701_bdp_drv = {
},
};
module_platform_driver(clk_mt2701_bdp_drv);
MODULE_DESCRIPTION("MediaTek MT2701 BDP clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-eth.c
View File

@ -60,4 +60,6 @@ static struct platform_driver clk_mt2701_eth_drv = {
},
};
module_platform_driver(clk_mt2701_eth_drv);
MODULE_DESCRIPTION("MediaTek MT2701 Ethernet clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-g3d.c
View File

@ -57,4 +57,6 @@ static struct platform_driver clk_mt2701_g3d_drv = {
},
};
module_platform_driver(clk_mt2701_g3d_drv);
MODULE_DESCRIPTION("MediaTek MT2701 GPU g3d clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-hif.c
View File

@ -57,4 +57,6 @@ static struct platform_driver clk_mt2701_hif_drv = {
},
};
module_platform_driver(clk_mt2701_hif_drv);
MODULE_DESCRIPTION("MediaTek MT2701 HIFSYS clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-img.c
View File

@ -54,4 +54,6 @@ static struct platform_driver clk_mt2701_img_drv = {
},
};
module_platform_driver(clk_mt2701_img_drv);
MODULE_DESCRIPTION("MediaTek MT2701 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-mm.c
View File

@ -87,4 +87,6 @@ static struct platform_driver clk_mt2701_mm_drv = {
.id_table = clk_mt2701_mm_id_table,
};
module_platform_driver(clk_mt2701_mm_drv);
MODULE_DESCRIPTION("MediaTek MT2701 MultiMedia ddp clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-vdec.c
View File

@ -59,4 +59,6 @@ static struct platform_driver clk_mt2701_vdec_drv = {
},
};
module_platform_driver(clk_mt2701_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT2701 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701.c
View File

@ -1037,4 +1037,6 @@ static int __init clk_mt2701_init(void)
}
arch_initcall(clk_mt2701_init);
MODULE_DESCRIPTION("MediaTek MT2701 main clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
View File

@ -163,4 +163,6 @@ static struct platform_driver clk_mt2712_apmixed_drv = {
},
};
module_platform_driver(clk_mt2712_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT2712 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-bdp.c
View File

@ -76,4 +76,6 @@ static struct platform_driver clk_mt2712_bdp_drv = {
},
};
module_platform_driver(clk_mt2712_bdp_drv);
MODULE_DESCRIPTION("MediaTek MT2712 BDP clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-img.c
View File

@ -54,4 +54,6 @@ static struct platform_driver clk_mt2712_img_drv = {
},
};
module_platform_driver(clk_mt2712_img_drv);
MODULE_DESCRIPTION("MediaTek MT2712 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-jpgdec.c
View File

@ -50,4 +50,6 @@ static struct platform_driver clk_mt2712_jpgdec_drv = {
},
};
module_platform_driver(clk_mt2712_jpgdec_drv);
MODULE_DESCRIPTION("MediaTek MT2712 JPEG Decoder clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-mfg.c
View File

@ -49,4 +49,6 @@ static struct platform_driver clk_mt2712_mfg_drv = {
},
};
module_platform_driver(clk_mt2712_mfg_drv);
MODULE_DESCRIPTION("MediaTek MT2712 GPU mfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-mm.c
View File

@ -128,4 +128,6 @@ static struct platform_driver clk_mt2712_mm_drv = {
.id_table = clk_mt2712_mm_id_table,
};
module_platform_driver(clk_mt2712_mm_drv);
MODULE_DESCRIPTION("MediaTek MT2712 MultiMedia ddp clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-vdec.c
View File

@ -62,4 +62,6 @@ static struct platform_driver clk_mt2712_vdec_drv = {
},
};
module_platform_driver(clk_mt2712_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT2712 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712-venc.c
View File

@ -51,4 +51,6 @@ static struct platform_driver clk_mt2712_venc_drv = {
},
};
module_platform_driver(clk_mt2712_venc_drv);
MODULE_DESCRIPTION("MediaTek MT2712 Video Encoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2712.c
View File

@ -1000,4 +1000,6 @@ static struct platform_driver clk_mt2712_drv = {
},
};
module_platform_driver(clk_mt2712_drv);
MODULE_DESCRIPTION("MediaTek MT2712 main clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765-audio.c
View File

@ -76,4 +76,6 @@ static struct platform_driver clk_mt6765_audio_drv = {
},
};
module_platform_driver(clk_mt6765_audio_drv);
MODULE_DESCRIPTION("MediaTek MT6765 audio clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765-cam.c
View File

@ -57,4 +57,6 @@ static struct platform_driver clk_mt6765_cam_drv = {
},
};
module_platform_driver(clk_mt6765_cam_drv);
MODULE_DESCRIPTION("MediaTek MT6765 Camera clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765-img.c
View File

@ -53,4 +53,6 @@ static struct platform_driver clk_mt6765_img_drv = {
},
};
module_platform_driver(clk_mt6765_img_drv);
MODULE_DESCRIPTION("MediaTek MT6765 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765-mipi0a.c
View File

@ -50,4 +50,6 @@ static struct platform_driver clk_mt6765_mipi0a_drv = {
},
};
module_platform_driver(clk_mt6765_mipi0a_drv);
MODULE_DESCRIPTION("MediaTek MT6765 Camera clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765-mm.c
View File

@ -79,4 +79,6 @@ static struct platform_driver clk_mt6765_mm_drv = {
},
};
module_platform_driver(clk_mt6765_mm_drv);
MODULE_DESCRIPTION("MediaTek MT6765 MultiMedia clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765-vcodec.c
View File

@ -52,4 +52,6 @@ static struct platform_driver clk_mt6765_vcodec_drv = {
},
};
module_platform_driver(clk_mt6765_vcodec_drv);
MODULE_DESCRIPTION("MediaTek MT6765 Video Codec clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6765.c
View File

@ -873,4 +873,6 @@ static int __init clk_mt6765_init(void)
}
arch_initcall(clk_mt6765_init);
MODULE_DESCRIPTION("MediaTek MT6765 main clocks driver");
MODULE_LICENSE("GPL");

3
drivers/clk/mediatek/clk-mt6779-aud.c
View File

@ -110,6 +110,7 @@ static struct platform_driver clk_mt6779_aud_drv = {
.of_match_table = of_match_clk_mt6779_aud,
},
};
module_platform_driver(clk_mt6779_aud_drv);
MODULE_DESCRIPTION("MediaTek MT6779 audio clocks driver");
MODULE_LICENSE("GPL");

3
drivers/clk/mediatek/clk-mt6779-cam.c
View File

@ -61,6 +61,7 @@ static struct platform_driver clk_mt6779_cam_drv = {
.of_match_table = of_match_clk_mt6779_cam,
},
};
module_platform_driver(clk_mt6779_cam_drv);
MODULE_DESCRIPTION("MediaTek MT6779 Camera clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779-img.c
View File

@ -55,4 +55,6 @@ static struct platform_driver clk_mt6779_img_drv = {
};
module_platform_driver(clk_mt6779_img_drv);
MODULE_DESCRIPTION("MediaTek MT6779 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779-ipe.c
View File

@ -57,4 +57,6 @@ static struct platform_driver clk_mt6779_ipe_drv = {
};
module_platform_driver(clk_mt6779_ipe_drv);
MODULE_DESCRIPTION("MediaTek MT6779 Image Processing Engine clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779-mfg.c
View File

@ -52,4 +52,6 @@ static struct platform_driver clk_mt6779_mfg_drv = {
};
module_platform_driver(clk_mt6779_mfg_drv);
MODULE_DESCRIPTION("MediaTek MT6779 GPU mfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779-mm.c
View File

@ -106,4 +106,6 @@ static struct platform_driver clk_mt6779_mm_drv = {
};
module_platform_driver(clk_mt6779_mm_drv);
MODULE_DESCRIPTION("MediaTek MT6779 MultiMedia mdp/ddp clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779-vdec.c
View File

@ -64,4 +64,6 @@ static struct platform_driver clk_mt6779_vdec_drv = {
};
module_platform_driver(clk_mt6779_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT6779 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779-venc.c
View File

@ -55,4 +55,6 @@ static struct platform_driver clk_mt6779_venc_drv = {
};
module_platform_driver(clk_mt6779_venc_drv);
MODULE_DESCRIPTION("MediaTek MT6779 Video Encoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6779.c
View File

@ -1330,4 +1330,6 @@ static int __init clk_mt6779_init(void)
}
arch_initcall(clk_mt6779_init);
MODULE_DESCRIPTION("MediaTek MT6779 main clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6795-mm.c
View File

@ -97,5 +97,5 @@ static struct platform_driver clk_mt6795_mm_drv = {
};
module_platform_driver(clk_mt6795_mm_drv);
MODULE_DESCRIPTION("MediaTek MT6795 MultiMedia clocks driver");
MODULE_DESCRIPTION("MediaTek MT6795 MMSYS clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6797-img.c
View File

@ -50,4 +50,6 @@ static struct platform_driver clk_mt6797_img_drv = {
},
};
module_platform_driver(clk_mt6797_img_drv);
MODULE_DESCRIPTION("MediaTek MT6797 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6797-mm.c
View File

@ -100,4 +100,6 @@ static struct platform_driver clk_mt6797_mm_drv = {
.id_table = clk_mt6797_mm_id_table,
};
module_platform_driver(clk_mt6797_mm_drv);
MODULE_DESCRIPTION("MediaTek MT6797 MultiMedia clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6797-vdec.c
View File

@ -61,4 +61,6 @@ static struct platform_driver clk_mt6797_vdec_drv = {
},
};
module_platform_driver(clk_mt6797_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT6797 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6797-venc.c
View File

@ -52,4 +52,6 @@ static struct platform_driver clk_mt6797_venc_drv = {
},
};
module_platform_driver(clk_mt6797_venc_drv);
MODULE_DESCRIPTION("MediaTek MT6797 Video Encoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt6797.c
View File

@ -708,4 +708,6 @@ static int __init clk_mt6797_init(void)
}
arch_initcall(clk_mt6797_init);
MODULE_DESCRIPTION("MediaTek MT6797 main clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7622-aud.c
View File

@ -156,4 +156,6 @@ static struct platform_driver clk_mt7622_aud_drv = {
},
};
module_platform_driver(clk_mt7622_aud_drv);
MODULE_DESCRIPTION("MediaTek MT7622 audio clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7622-eth.c
View File

@ -86,4 +86,6 @@ static struct platform_driver clk_mt7622_eth_drv = {
},
};
module_platform_driver(clk_mt7622_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7622 Ethernet clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7622-hif.c
View File

@ -98,4 +98,6 @@ static struct platform_driver clk_mt7622_hif_drv = {
},
};
module_platform_driver(clk_mt7622_hif_drv);
MODULE_DESCRIPTION("MediaTek MT7622 HIF clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7629-eth.c
View File

@ -157,4 +157,6 @@ static struct platform_driver clk_mt7629_eth_drv = {
};
builtin_platform_driver(clk_mt7629_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7629 Ethernet clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7629-hif.c
View File

@ -93,4 +93,6 @@ static struct platform_driver clk_mt7629_hif_drv = {
},
};
module_platform_driver(clk_mt7629_hif_drv);
MODULE_DESCRIPTION("MediaTek MT2701 HIF clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7629.c
View File

@ -698,4 +698,6 @@ static int clk_mt7629_init(void)
}
arch_initcall(clk_mt7629_init);
MODULE_DESCRIPTION("MediaTek MT7629 main clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7981-apmixed.c
View File

@ -99,4 +99,6 @@ static struct platform_driver clk_mt7981_apmixed_drv = {
},
};
builtin_platform_driver(clk_mt7981_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT7981 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7981-eth.c
View File

@ -114,4 +114,6 @@ static struct platform_driver clk_mt7981_eth_drv = {
},
};
module_platform_driver(clk_mt7981_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7981 Ethernet clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7981-infracfg.c
View File

@ -204,4 +204,6 @@ static struct platform_driver clk_mt7981_infracfg_drv = {
},
};
module_platform_driver(clk_mt7981_infracfg_drv);
MODULE_DESCRIPTION("MediaTek MT7981 infracfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7981-topckgen.c
View File

@ -420,4 +420,6 @@ static struct platform_driver clk_mt7981_topckgen_drv = {
},
};
module_platform_driver(clk_mt7981_topckgen_drv);
MODULE_DESCRIPTION("MediaTek MT7981 top clock generators driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7986-apmixed.c
View File

@ -97,4 +97,6 @@ static struct platform_driver clk_mt7986_apmixed_drv = {
},
};
builtin_platform_driver(clk_mt7986_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT7986 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7986-topckgen.c
View File

@ -313,4 +313,6 @@ static struct platform_driver clk_mt7986_topckgen_drv = {
},
};
module_platform_driver(clk_mt7986_topckgen_drv);
MODULE_DESCRIPTION("MediaTek MT7986 top clock generators driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7988-apmixed.c
View File

@ -111,4 +111,6 @@ static struct platform_driver clk_mt7988_apmixed_drv = {
},
};
builtin_platform_driver(clk_mt7988_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT7988 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7988-infracfg.c
View File

@ -295,4 +295,6 @@ static struct platform_driver clk_mt7988_infracfg_drv = {
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_infracfg_drv);
MODULE_DESCRIPTION("MediaTek MT7988 infracfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt7988-topckgen.c
View File

@ -322,4 +322,6 @@ static struct platform_driver clk_mt7988_topckgen_drv = {
},
};
module_platform_driver(clk_mt7988_topckgen_drv);
MODULE_DESCRIPTION("MediaTek MT7988 top clock generators driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
View File

@ -142,4 +142,6 @@ static struct platform_driver clk_mt8167_apmixed_drv = {
},
};
builtin_platform_driver(clk_mt8167_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8167 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167-aud.c
View File

@ -61,4 +61,6 @@ static struct platform_driver clk_mt8167_audsys_drv = {
},
};
module_platform_driver(clk_mt8167_audsys_drv);
MODULE_DESCRIPTION("MediaTek MT8167 audio clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167-img.c
View File

@ -53,4 +53,6 @@ static struct platform_driver clk_mt8167_imgsys_drv = {
},
};
module_platform_driver(clk_mt8167_imgsys_drv);
MODULE_DESCRIPTION("MediaTek MT8167 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167-mfgcfg.c
View File

@ -51,4 +51,6 @@ static struct platform_driver clk_mt8167_mfgcfg_drv = {
},
};
module_platform_driver(clk_mt8167_mfgcfg_drv);
MODULE_DESCRIPTION("MediaTek MT8167 GPU mfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167-mm.c
View File

@ -92,4 +92,6 @@ static struct platform_driver clk_mt8167_mm_drv = {
.id_table = clk_mt8167_mm_id_table,
};
module_platform_driver(clk_mt8167_mm_drv);
MODULE_DESCRIPTION("MediaTek MT8167 MultiMedia clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167-vdec.c
View File

@ -60,4 +60,6 @@ static struct platform_driver clk_mt8167_vdec_drv = {
},
};
module_platform_driver(clk_mt8167_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT8167 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8167.c
View File

@ -894,4 +894,6 @@ static struct platform_driver clk_mt8167_drv = {
},
};
module_platform_driver(clk_mt8167_drv);
MODULE_DESCRIPTION("MediaTek MTì8167 main clocks driver");
MODULE_LICENSE("GPL");

12
drivers/clk/mediatek/clk-mt8173-infracfg.c
View File

@ -98,7 +98,17 @@ CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
static int clk_mt8173_infracfg_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
int r;
int r, i;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
if (!infra_clk_data)
return -ENOMEM;
} else {
for (i = 0; i < CLK_INFRA_NR_CLK; i++)
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
r = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
ARRAY_SIZE(infra_gates), infra_clk_data);

2
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
View File

@ -192,4 +192,6 @@ static struct platform_driver clk_mt8183_apmixed_drv = {
},
};
builtin_platform_driver(clk_mt8183_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8183 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-audio.c
View File

@ -108,4 +108,6 @@ static struct platform_driver clk_mt8183_audio_drv = {
},
};
module_platform_driver(clk_mt8183_audio_drv);
MODULE_DESCRIPTION("MediaTek MT8183 audio clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-cam.c
View File

@ -58,4 +58,6 @@ static struct platform_driver clk_mt8183_cam_drv = {
},
};
module_platform_driver(clk_mt8183_cam_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Camera clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-img.c
View File

@ -58,4 +58,6 @@ static struct platform_driver clk_mt8183_img_drv = {
},
};
module_platform_driver(clk_mt8183_img_drv);
MODULE_DESCRIPTION("MediaTek MT8183 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-ipu0.c
View File

@ -51,4 +51,6 @@ static struct platform_driver clk_mt8183_ipu_core0_drv = {
},
};
module_platform_driver(clk_mt8183_ipu_core0_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Pri. Image Processing Unit clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-ipu1.c
View File

@ -51,4 +51,6 @@ static struct platform_driver clk_mt8183_ipu_core1_drv = {
},
};
module_platform_driver(clk_mt8183_ipu_core1_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Sec. Image Processing Unit clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-ipu_adl.c
View File

@ -49,4 +49,6 @@ static struct platform_driver clk_mt8183_ipu_adl_drv = {
},
};
module_platform_driver(clk_mt8183_ipu_adl_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Image Processing Unit ADL driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
View File

@ -118,4 +118,6 @@ static struct platform_driver clk_mt8183_ipu_conn_drv = {
},
};
module_platform_driver(clk_mt8183_ipu_conn_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Image Processing Unit Bus clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-mfgcfg.c
View File

@ -50,4 +50,6 @@ static struct platform_driver clk_mt8183_mfg_drv = {
},
};
module_platform_driver(clk_mt8183_mfg_drv);
MODULE_DESCRIPTION("MediaTek MT8183 GPU mfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-mm.c
View File

@ -102,4 +102,6 @@ static struct platform_driver clk_mt8183_mm_drv = {
.id_table = clk_mt8183_mm_id_table,
};
module_platform_driver(clk_mt8183_mm_drv);
MODULE_DESCRIPTION("MediaTek MT8183 MultiMedia clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-vdec.c
View File

@ -62,4 +62,6 @@ static struct platform_driver clk_mt8183_vdec_drv = {
},
};
module_platform_driver(clk_mt8183_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183-venc.c
View File

@ -54,4 +54,6 @@ static struct platform_driver clk_mt8183_venc_drv = {
},
};
module_platform_driver(clk_mt8183_venc_drv);
MODULE_DESCRIPTION("MediaTek MT8183 Video Encoders clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8183.c
View File

@ -906,4 +906,6 @@ static struct platform_driver clk_mt8183_drv = {
},
};
module_platform_driver(clk_mt8183_drv)
MODULE_DESCRIPTION("MediaTek MT8183 main clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-apmixedsys.c
View File

@ -192,4 +192,6 @@ static struct platform_driver clk_mt8186_apmixed_drv = {
},
};
module_platform_driver(clk_mt8186_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT8186 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-cam.c
View File

@ -89,4 +89,6 @@ static struct platform_driver clk_mt8186_cam_drv = {
},
};
module_platform_driver(clk_mt8186_cam_drv);
MODULE_DESCRIPTION("MediaTek MT8186 Camera clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-img.c
View File

@ -67,4 +67,6 @@ static struct platform_driver clk_mt8186_img_drv = {
},
};
module_platform_driver(clk_mt8186_img_drv);
MODULE_DESCRIPTION("MediaTek MT8186 imgsys clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c
View File

@ -66,4 +66,6 @@ static struct platform_driver clk_mt8186_imp_iic_wrap_drv = {
},
};
module_platform_driver(clk_mt8186_imp_iic_wrap_drv);
MODULE_DESCRIPTION("MediaTek MT8186 I2C Wrapper clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-infra_ao.c
View File

@ -238,4 +238,6 @@ static struct platform_driver clk_mt8186_infra_ao_drv = {
},
};
module_platform_driver(clk_mt8186_infra_ao_drv);
MODULE_DESCRIPTION("MediaTek MT8186 infracfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-ipe.c
View File

@ -54,4 +54,6 @@ static struct platform_driver clk_mt8186_ipe_drv = {
},
};
module_platform_driver(clk_mt8186_ipe_drv);
MODULE_DESCRIPTION("MediaTek MT8186 Image Processing Engine clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-mdp.c
View File

@ -79,4 +79,6 @@ static struct platform_driver clk_mt8186_mdp_drv = {
},
};
module_platform_driver(clk_mt8186_mdp_drv);
MODULE_DESCRIPTION("MediaTek MT8186 Multimedia Data Path clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-mfg.c
View File

@ -48,4 +48,6 @@ static struct platform_driver clk_mt8186_mfg_drv = {
},
};
module_platform_driver(clk_mt8186_mfg_drv);
MODULE_DESCRIPTION("MediaTek MT8186 GPU mfg clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-mm.c
View File

@ -78,4 +78,6 @@ static struct platform_driver clk_mt8186_mm_drv = {
.id_table = clk_mt8186_mm_id_table,
};
module_platform_driver(clk_mt8186_mm_drv);
MODULE_DESCRIPTION("MediaTek MT8186 MultiMedia clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt8186-topckgen.c
View File

@ -732,4 +732,6 @@ static struct platform_driver clk_mt8186_topck_drv = {
},
};
module_platform_driver(clk_mt8186_topck_drv);
MODULE_DESCRIPTION("MediaTek MT8186 top clock generators driver");
MODULE_LICENSE("GPL");

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